Advertisement

Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs

  • Nuno Roma
  • Tiago Dias
  • Leonel Sousa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper proposes new core-based architectures for motion estimation that are customisable for different coding parameters and hardware resources. These new cores are derived from an efficient and fully parameterisable 2-D single array systolic structure for full-search block-matching motion estimation and inherit its configurability properties in what concerns the macroblock dimension, the search area and parallelism level. The proposed architectures require significantly fewer hardware resources, by reducing the spatial and pixel resolutions rather than restricting the set of considered candidate motion vectors. Low-cost and low-power regular architectures suitable for field programmable logic implementation are obtained without compromising the quality of the coded video sequences. Experimental results show that despite the significant complexity level presented by motion estimation processors, it is still possible to implement fast and low-cost versions of the original core-based architecture using general purpose FPGA devices.

Keywords

Motion Estimation Field Programmable Gate Array Hardware Resource Motion Estimation Algorithm Quantisation Step Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bhaskaran, V., Konstantinides, K.: Image and Video Compression Standards: Algorithms and Architectures, 2nd edn. Kluwer Academic Publishers, Dordrecht (1997)CrossRefGoogle Scholar
  2. 2.
    Koga, T., Iinuma, K., Hirano, A., Iijima, Y., Ishiguro, T.: Motion-compensated interframe coding for video conferencing. In: Proc. Nat. Telecomm. Conference, New Orleans, LA, pp. G5.3.1–G5.3.5 (1981)Google Scholar
  3. 3.
    Jain, J.R., Jain, A.K.: Displacement measurement and its application in interframe image coding. IEEE Transactions on Communications COM-29, 1799–1808 (1981)CrossRefGoogle Scholar
  4. 4.
    Roma, N., Sousa, L.: Efficient and configurable full search block matching processors. IEEE Transactions on Circuits and Systems for Video Technology 12, 1160–1167 (2002)CrossRefGoogle Scholar
  5. 5.
    Ooi, Y.: Motion estimation system design. In: Parhi, K.K., Nishitani, T. (eds.) Digital Signal Processing for Multimedia Systems, pp. 299–327. Marcel Dekker, Inc., New York (1999)Google Scholar
  6. 6.
    Vos, L., Stegherr, M.: Parameterizable VLSI architectures for the full-search block-matching algorithm. IEEE Transactions on Circuits and Systems 36, 1309–1316 (1989)CrossRefGoogle Scholar
  7. 7.
    Liu, B., Zaccarin, A.: New fast algorithms for the estimation of block matching vectors. IEEE Transactions on Circuits and Systems for Video Technology 3, 148–157 (1993)CrossRefGoogle Scholar
  8. 8.
    Ogura, E., Ikenaga, Y., Iida, Y., Hosoya, Y., Takashima, M., Yamash, K.: A cost effective motion estimation processor LSI using a simple and efficient algorithm. In: Proceedings of International Conference on Consumer Electronics - ICCE, pp. 248–249 (1995)Google Scholar
  9. 9.
    Lee, S., Kim, J.M., Chae, S.I.: New motion estimation algorithm using adaptively-quantized low bit resolution image and its vlsi architecture for MPEG2 video coding. IEEE Transactions on Circuits and Systems for Video Technology 8, 734–744 (1998)CrossRefGoogle Scholar
  10. 10.
    He, Z.L., Chan, K.K., Tsui, C.Y., Liou, M.L.: Low power motion estimation design using adaptative pixel truncation. In: Proceedings of the, international symposium on Low power electronics and design, Monterey - USA, pp. 167–171 (1997)Google Scholar
  11. 11.
    Telenor Research Norway: TMN (H.263) encoder/decoder, version 2.0 (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Nuno Roma
    • 1
  • Tiago Dias
    • 1
  • Leonel Sousa
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringInstituto Superior Técnico / INESC-IDLisboaPortugal

Personalised recommendations