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A New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation

  • Chang Hoon Kim
  • Soonhak Kwon
  • Jong Jin Kim
  • Chun Pyo Hong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper proposes a new arithmetic unit (AU) in GF(2m) for reconfigurable hardware implementation such as FPGAs, which overcomes the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions. The proposed AU performs both division and multiplication in GF(2m). These operations are at the heart of elliptic curve cryptosystems (ECC). Analysis shows that the proposed AU has significantly less area complexity and has roughly the same or lower latency compared with some related circuits. In addition, we show that the proposed architecture preserves a high clock rate for large m (up to 571), when it is implemented on Altera’s EP2A70F1508C-7 FPGA device. Furthermore, the new architecture provides a high flexibility and scalability with respect to the field size m, since it does not restrict the choice of irreducible polynomials and has the features of regularity, modularity, and unidirectional data flow. Therefore, the proposed architecture is well suited for both division and multiplication unit of ECC implemented on FPGAs.

Keywords

Finite Field Division Finite Field Multiplication ECC VLSI 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Chang Hoon Kim
    • 1
  • Soonhak Kwon
    • 2
  • Jong Jin Kim
    • 1
  • Chun Pyo Hong
    • 1
  1. 1.Dept. of Computer and Information EngineeringDaegu UniversityJinryang, KyungsanKorea
  2. 2.Dept. of Mathematics and Inst. of Basic ScienceSungkyunkwan UniversitySuwonKorea

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