The Bank Nth Chance Replacement Policy for FPGA-Based CAMs

  • Paul Berube
  • Ashley Zinyk
  • José Nelson Amaral
  • Mike MacGregor
Conference paper
Part of the Lecture Notes in Computer Science book series (volume 2778)


In this paper we describe a method to implement a large, high density, fully associative cache in the Xilinx VirtexE FPGA architecture. The cache is based on a content addressable memory (CAM), with an associated memory to store information for each entry, and a replacement policy for victim selection. This implementation method is motivated by the need to improve the speed of routing of IP packets through Internet routers. To test our methodology, we designed a prototype cache with a 32 bit cache tag for the IP address and 4 bits of associated data for the forwarding information. The number of cache entries and the sizes of the data fields are limited by the area available in the FPGA. However, these sizes are specified as high level design parameters, which makes modifying the design for different cache configurations or larger devices trivial.


field programmable gate array cache memories replacement policy multizone cache content addressable memories Internet routing digital design memory systems 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Paul Berube
    • 1
  • Ashley Zinyk
    • 1
  • José Nelson Amaral
    • 1
  • Mike MacGregor
    • 1
  1. 1.Dept. of Computer ScienceUniversity of AlbertaEdmontonCanada

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