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Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits

  • M. Sonza Reorda
  • M. Violante
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The continuous technology scaling makes soft errors a critical issue in deep sub-micron technologies, and techniques for assessing their impact are strongly required that combine efficiency and accuracy. FPGA-based emulation is a promising solution to tackle this problem when large circuits are considered, provided that suitable techniques are available to support time-accurate simulations via emulation. This paper presents a novel technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of the soft errors known as single event transients (SETs) in large circuits via FPGA-based emulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time, as showed by the case study described in the paper.

Keywords

Fault Injection Soft Error Circuit Input Fault List Single Event Transient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Anghel, L., Nicolaidis, M.: Cost Reduction of a Temporary Faults Detecting Technique. In: DATE 2000: ACM/IEEE Design, Automation and Test in Europe Conference, pp. 591–598 (2000)Google Scholar
  2. 2.
    Constantinescu, C.: Impact of deep submicron technology on dependability of VLSI circuits. In: Proc. IEEE Int. Conference on Dependable Systems and Networks, pp. 205–209 (2002)Google Scholar
  3. 3.
    Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modelling the effect of technology trends on the soft error rate of combinational logic. In: Proc. IEEE Int. Conference on Dependable Systems and Networks, pp. 389–398 (2002)Google Scholar
  4. 4.
    Hsueh, M.-C., Tsai, T.K., Iyer, R.K.: Fault injection techniques and tools. IEEE Computer 30(4), 75–82 (1997)CrossRefGoogle Scholar
  5. 5.
    Dahlgren, P., Liden, P.: A switch-level algorithm for simulation of transients in combination logic. In: Proc. Fault Tolerant Computing Symposium, pp. 207–216 (1995)Google Scholar
  6. 6.
    Jenn, E., Arlat, J., Rimen, M., Ohlsson, J., Karlsson, J.: Fault Injection into VHDL Models: the MEFISTO Tool. In: Proc. Fault Tolerant Computing Symposium, pp. 66–75 (1994)Google Scholar
  7. 7.
    Delong, T.A., Johnson, B.W., Profeta III, J.A.: A Fault Injection Technique for VHDL Behavioral-Level Models. IEEE Design & Test of Computers, 24–33 (Winter 1996)Google Scholar
  8. 8.
    Gil, D., Martinez, R., Busquets, J.V., Baraza, J.C., Gil, P.J.: Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. In: European Conference of Dependable Computing (EDCC-3), pp. 191–208 (1999)Google Scholar
  9. 9.
    Boué, J., Pétillon, P., Crouzet, Y.: MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance. In: Proc. Fault-Tolerant Computing Symposium, pp. 168-173 (1998)Google Scholar
  10. 10.
    Civera, P., Macchiarulo, L., Rebaudengo, M., Sonza Reorda, M., Violante, M.: Exploiting Circuit Emulation for Fast Hardness Evaluation. IEEE Transactions on Nuclear Science 48(6), 2210–2216 (2001)CrossRefGoogle Scholar
  11. 11.
    Antoni, L., Leveugle, R., Fehér, B.: Using run-time reconfiguration for fault injection in hardware prototypes. In: Proc. IEEE Int.l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 405–413 (2000)Google Scholar
  12. 12.
    Massengill, L.W., Baranski, A.E., Van Nort, D.O., Meng, J., Bhuva, B.L.: Analysis of Single-Event Effects in Combinational Logic-Simulation of the AM2901 Bitslice Processor. IEEE Transactions on Nuclear Science 47(6), 2609–2615 (2000)CrossRefGoogle Scholar
  13. 13.
    Berrojo, L., González, I., Corno, F., Sonza Reorda, M., Squillero, G., Entrena, L., Lopez, C.: New Techniques for Speeding-up Fault-injection Campaigns. In: Proc. IEEE Design, Automation and Test in Europe, pp. 847–852 (2002)Google Scholar
  14. 14.
    Hass, K.J., Gambles, J.W.: Single event transients in deep submicron CMOS. In: IEEE 42nd Midwest Symposium on Circuits and Systems, pp. 122–125 (1999)Google Scholar
  15. 15.
    Manich, S., Figueras, J.: Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. In: Proc. IEEE European Design and Test Conference, pp. 597–602 (1997)Google Scholar
  16. 16.
    ADM-XRC PCI Mezzanine card User Guide Version 1.2, http://www.alphadata.co.uk/
  17. 17.
    Parrotta, B., Rebaudengo, M., Sonza Reorda, M., Violante, M.: New Techniques for Accelerating Fault Injection in VHDL descriptions. In: IEEE Int.l On-Line Testing Workshop, pp. 61–66 (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • M. Sonza Reorda
    • 1
  • M. Violante
    • 1
  1. 1.Dip. Automatica e InformaticaPolitecnico di TorinoTorinoItaly

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