Advertisement

Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements

  • Unai Bidarte
  • Armando Astarloa
  • Aitzol Zuloaga
  • Jaime Jimenez
  • Iñigo Martínez de Alegría
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Many digital circuit’s functionality is strongly dependant on high speed data exchange between data source and sink elements. In order to alleviate the main processor’s work, it is usually interesting to isolate high speed data exchange from all other control tasks. A generic architecture, based on configurable cores, has been achieved for slave circuits controlled by an external host and with extensive data exchange requirements. Design reuse has been improved by means of a software application that helps on configuration and simulation tasks. Two applications implemented on FPGA technology are presented to validate the proposed architecture.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Cesrio, W., Baghdadi, A.: Component-Based Design Approach for Multicore SoCs. Design Automation Conference. In: Proceedings of the 39th conference, New Orleans, Louisiana (2002)Google Scholar
  2. 2.
    Bergamaschi, R., Lee, W.: Designing Systems on Chip Using Cores. Design Automation Conference. In: Proceedings of the 37th conference (2000)Google Scholar
  3. 3.
    Gupta, R., Zorian, Y.: Introducing core-based system design. IEEE Design and Test of Computers, pp. 15–25 (October-December 1997) CrossRefGoogle Scholar
  4. 4.
    Xilinx Design Reuse Methodology for ASIC and FPGA Designers, http://www.xilinx.com/ipcenter/designreuse/docs/Xilinx-Design-Reuse-Methodology.pdf
  5. 5.
    Bursky, D.: Core-based design leads the way to flexible system solutions. Electronic Design (May 1997)Google Scholar
  6. 6.
    Balarin, F.: Hardware-Software Co-design of Embedded Systems: The POLIS approach. Kluwer Academic Press, Dordrecht (1997)CrossRefGoogle Scholar
  7. 7.
  8. 8.
    Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores (rev. B.2), Silicore Corporation, Corcoran (USA) (October 2001)Google Scholar
  9. 9.
    Gleerup, T.: Memory Architecture for Efficient Utilization of SDRAM: A Case Study of the Computation/Memory Access Trade Off. In: Int’l Workshop on Hardware-software Codesign, pp. 51–55 (2000)Google Scholar
  10. 10.
    Quinnell, R.: Development tool suits core-based design. Electronic Design (August 1996)Google Scholar
  11. 11.
    Chakrabarty, K.: Optimal test access architectures for system-on-a-chip. Transactions on Design Automation of Electronic Systems, 26–49 (January 2001)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Unai Bidarte
    • 1
  • Armando Astarloa
    • 1
  • Aitzol Zuloaga
    • 1
  • Jaime Jimenez
    • 1
  • Iñigo Martínez de Alegría
    • 1
  1. 1.Department of Electronics and TelecommunicationsUniversity of the Basque Country, E.T.S. IngenierosBilbaoSpain

Personalised recommendations