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A Model for Hardware Realization of Kernel Loops

  • Jirong Liao
  • Weng-Fai Wong
  • Tulika Mitra
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In this paper, we consider two important loop optimization techniques, namely loop unrolling and software pipelining that can impact the performance and cost of the synthesized hardware. We propose a novel model that accounts for various characteristics of a loop, including dependencies, parallelism and resource requirement, as well as certain high level constraints of the implementation platform. Using this model, we are able to deduce the optimal unroll factor and technique for achieving the best performance given a fixed resource budget. The model was verified using a compiler-based FPGA synthesis framework on a number of kernel loops. We believe that our model is general and applicable to other synthesis frameworks, and will help reduce the time for design space exploration.

Keywords

Design Space Exploration Schedule Length Hardware Realization Software Pipeline Loop Unroll 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jirong Liao
    • 1
  • Weng-Fai Wong
    • 1
  • Tulika Mitra
    • 1
  1. 1.Department of Computer Science, School of ComputingNational University of SingaporeSingapore

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