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Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA

  • François Charot
  • Eslam Yahya
  • Charles Wagner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper describes a high performance single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks and operating in Counter (CTR) mode. Counter mode has a proven-tight security and it enables the simultaneous processing of multiple blocks without losing the feedback mode advantages. It also gives the advantage of allowing the use of similar hardware for both encryption and decryption parts. The proposed architecture is modular. The architecture basic module implements a single round of the algorithm with the required expansion hardware and control signals. It gives very high flexibility in choosing the degree of pipelining according to the throughput requirements and hardware limitations and this gives the ability to achieve the best compromised design due to these aspects. The FPGA implementation presented is that of a pipelined single chip Rijndael design which runs at a rate of 10.8 Gbits/sec for full pipelining on an ALTERA APEX-EP20KE platform.

Keywords

Block Cipher Advance Encryption Standard FPGA Implementation Input Block Decryption Part 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • François Charot
    • 1
  • Eslam Yahya
    • 2
  • Charles Wagner
    • 1
  1. 1.IRISA/INRIA Campus de BeaulieuRennes CedexFrance
  2. 2.Information Technology Institute-ITIBenha High Institute of Technology-BHITBenhaEgypt

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