Exploiting Redundancy to Speedup Reconfiguration of an FPGA

  • Irwin Kennedy
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


Reconfigurable logic promises a flexible computing fabric well suited to the low cost, low power, high performance and fast time to market demanded of today’s computing devices. This paper presents an analysis of what exactly occurs when a fine grain FPGA, specifically the Xilinx Virtex, is reconfigured, and proposes a tailorable approach to configuration architecture design trading off silicon area with reconfiguration time. It is shown that less than 3% of the bits contained in a typical Virtex reconfiguration bitstream are different to those already in the configuration memory, and a highly parallelisable compression technique is presented which achieves highly competitive results – 80% compression and better.


Compression Algorithm Compression Technique Silicon Area Overlay Technique Control Circuitry 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Zhiyuan, L., Hauck, S.: Configuration Compression for Virtex FPGAs. In: IEEE Symposium on FPGAs for Custom Computing Machines (April 2001)Google Scholar
  2. 2.
    Motomura, M., Aimoto, Y., Shibayama, A., Yabe, Y., Yamashina, M.: An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In: Symposium on VLSI Circuits Digest of Technical Papers, June 1997, pp. 55–56 (1997)Google Scholar
  3. 3.
    Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A time multiplexed FPGA. In: IEEE Symposium on Field-Programmable Custom Computing Machines (April 1997)Google Scholar
  4. 4.
    Xilinx Corporation, Virtex 2.5V Field-Programmable Gate Arrays, DS003-1 (v.25) April 2 (2001)Google Scholar
  5. 5.
    Xilinx Corporation, Virtex Series Configuration Architecture User Guide, XAPP151 (v1.5), September 27 (2000)Google Scholar
  6. 6.
    Franklin, N.: Re: Silicon Area for Xilinx FPGAs. comp.arch.fpga, PST 5, 31–59 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Irwin Kennedy
    • 1
  1. 1.Division of InformaticsUniversity of EdinburghEdinburghUK

Personalised recommendations