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Low Power Coarse-Grained Reconfigurable Instruction Set Processor

  • Francisco Barat
  • Murali Jayapala
  • Tom Vander Aa
  • Rudy Lauwereins
  • Geert Deconinck
  • Henk Corporaal
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Current embedded multimedia applications have stringent time and power constraints. Coarse-grained reconfigurable processors have been shown to achieve the required performance. However, there is not much research regarding the power consumption of such processors. In this paper, we present a novel coarse-grained reconfigurable processor and study its power consumption using a power model derived from Wattch. Several processor configurations are evaluated using a set of multimedia applications. Results show that the presented coarse-grained processor can achieve on average 2.5x the performance of a RISC processor with an 18% increase in energy consumption.

Keywords

Power Consumption Functional Unit Processing Element Multimedia Application RISC Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Francisco Barat
    • 1
  • Murali Jayapala
    • 1
  • Tom Vander Aa
    • 1
  • Rudy Lauwereins
    • 1
    • 2
  • Geert Deconinck
    • 1
  • Henk Corporaal
    • 3
  1. 1.ESATK.U.LeuvenLeuven-HeverleeBelgium
  2. 2.TUEindhovenEindhovenThe Netherlands
  3. 3.ImecLeuvenBelgium

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