Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm

  • Ivan Gonzalez
  • Sergio Lopez-Buedo
  • Francisco J. Gomez
  • Javier Martinez
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper shows that partial reconfiguration can notably improve the area and throughput of symmetric cryptographic algorithms implemented in FPGAs. In most applications the keys are fixed during a cipher session, so that several blocks, like module adders or multipliers, can be substituted for their constant-operand equivalents. These counterparts not only are faster, but also use significantly less resources. In this approach, the changes in the key are performed through a partial reconfiguration that modifies the constants. The International Data Encryption Algorithm (IDEA) has been selected as a case-study, and JBits has been chosen as the tool for performing the partial reconfiguration. The implementation occupies an 87% of a Virtex XCV600 and achieves a throughput of 8.3 GBits/sec.


Pipeline Stage Partially Evaluate Cryptographic Application Partial Reconfiguration Virtex FPGAs 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ivan Gonzalez
    • 1
  • Sergio Lopez-Buedo
    • 1
  • Francisco J. Gomez
    • 1
  • Javier Martinez
    • 1
  1. 1.Escuela Politecnica SuperiorUniversidad Autonoma de MadridMadridSpain

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