Advertisement

Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm

  • Ivan Gonzalez
  • Sergio Lopez-Buedo
  • Francisco J. Gomez
  • Javier Martinez
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper shows that partial reconfiguration can notably improve the area and throughput of symmetric cryptographic algorithms implemented in FPGAs. In most applications the keys are fixed during a cipher session, so that several blocks, like module adders or multipliers, can be substituted for their constant-operand equivalents. These counterparts not only are faster, but also use significantly less resources. In this approach, the changes in the key are performed through a partial reconfiguration that modifies the constants. The International Data Encryption Algorithm (IDEA) has been selected as a case-study, and JBits has been chosen as the tool for performing the partial reconfiguration. The implementation occupies an 87% of a Virtex XCV600 and achieves a throughput of 8.3 GBits/sec.

Keywords

Pipeline Stage Partially Evaluate Cryptographic Application Partial Reconfiguration Virtex FPGAs 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Beuchat, J.L., Haenni, J.O., Restrepo, H.F., Teuscher, C., Gomez, F.J., Sanchez, E.: Approches matérielles et logicielles de l’algorithme de chiffrement IDEA. Technique et Science Informatiques (TSI) 1, 203–224 (2001) (in French)Google Scholar
  2. 2.
    Hämäläin, A., Tommiska, M., Skyttä, J.: 6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 760–769. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  3. 3.
    Leong, M.P., Cheung, O.Y.H., Tsoi, K.H., Leong, P.H.W.: A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. In: Proc. 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, pp. 122–131 (2000)Google Scholar
  4. 4.
    Cheung, O.Y.H., Soi, K.H.T., Leong, P.H.W., Leong, M.P.: Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 333–347. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  5. 5.
    Patterson, C.: High Perfomance DES Encryption in Virtex FPGAs using JBits. In: Proc. 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, pp. 113–121 (2000)Google Scholar
  6. 6.
    Leonard, J., Magione-Smith, W.: A Case Study of Partially Evaluated Hardware Circuits: Key-Specific DES. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, Springer, Heidelberg (1997)Google Scholar
  7. 7.
    Daemen, J., Rijmen, V.: AES Proposal: Rijndael. NIST AES Proposal (1998)Google Scholar
  8. 8.
  9. 9.
    James-Roxby, P., Blodget, B.J.: A Study of high-perfomance reconfigurable constant coefficient multiplier implementations, Xilinx Inc., Tech Notes Archive Chipcenter, http://www.chipcenter.com/pld/images/pldf085.pdf
  10. 10.
    Leong, P.H.W., Leung, K.H.: A Microcoded Elliptic Curve Processor using FPGA Technology. IEEE Transactions on VLSI Systems (2002) (accepted for publication)Google Scholar
  11. 11.
  12. 12.
    Guccione, S.A., Levi, D.: JBits: A Java-based Interface to FPGA Hardware. Xilinx Inc., San Jose (1998)Google Scholar
  13. 13.
    Guccione, S.A., Levi, D., Sundararajan, P.: Java-based Interface for Reconfigurable Computing. In: Proc. 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD)Google Scholar
  14. 14.
    Guccione, S.A., Levi, D.: Run-Time Parameterizable Cores. Xilinx Inc., San Jose (1999)Google Scholar
  15. 15.
    McMillian, S., Guccione, S.A.: Partial Run-Time Reconfiguration using JRTR. Xilinx Inc., San Jose (2000)Google Scholar
  16. 16.
    Gonzalez, I.: Codiseño en Sistemas Reconfigurables basado en Java., Internal Technical Report, UAM, Madrid (2002) (in Spanish)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ivan Gonzalez
    • 1
  • Sergio Lopez-Buedo
    • 1
  • Francisco J. Gomez
    • 1
  • Javier Martinez
    • 1
  1. 1.Escuela Politecnica SuperiorUniversidad Autonoma de MadridMadridSpain

Personalised recommendations