Domain-Specific Reconfigurable Array for Distributed Arithmetic

  • Sami Khawam
  • Tughrul Arslan
  • Fred Westall
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Cosine Transform. This paper presents a flexible, low-power and high throughput array for implementing distributed arithmetic computations. Flexibility is achieved by using an array of elements arranged in an interconnect mesh similar to those employed in conventional FPGA architectures. We provide results which demonstrate a significant reduction in power consumption in addition to improvements in timing and area over standard FPGA architectures.


Embedded reconfigurable array programmable distributed arithmetic FPGA domain specific low-power 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Sami Khawam
    • 1
  • Tughrul Arslan
    • 1
    • 2
  • Fred Westall
    • 3
  1. 1.School of Electronic and EngineeringThe University of Edinburgh, KBEdinburghUK
  2. 2.Institute for System Level IntegrationLivingstonUK
  3. 3.EPSON Scotland Design CentreLivingstonUK

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