Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures
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With technology improvements, the main bottleneck in terms of performance, power consumption, and design reuse in single chip systems is proving to be generated by the on-chip communication architecture. Benefiting from the non-uniformity of the workload in various signal processing applications, several dynamic power management policies can be envisaged. Nevertheless, the integration of on-line power, performance and information-flow management strategies based on traffic monitoring in (dynamically) reconfigurable templates has yet to be explicitly tackled. The main objective of this work is to define the concept of run-time functional optimization of application specific standard products, and show the importance of integrating such techniques in reconfigurable platforms and especially their communication architectures.
KeywordsInterconnection Network Communication Architecture Dynamic Power Management Design Reuse Power Management Policy
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- 2.Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. IEEE Computer, 70–78 (January 2002)Google Scholar
- 3.Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks. In: An Engineering Approach. Morgan Kaufmann Publishers, San Francisco (2003)Google Scholar
- 4.Hartenstein, R.: A Decade of Reconfigurable Computing: A Visionary Retrospective. In: Proc. of DATE, pp. 642–649 (2001)Google Scholar
- 6.Murgan, T., García Ortiz, A., Petrov, M., Glesner, M.: A Stochastic Framework for Communication Architecture Evaluation in Networks-on-Chip. In: IEEE Intl. Symposium on Signals, Circuits and Systems (July 2003)Google Scholar
- 7.Seitz, C.: Let’s Route Packets Instead of Wires. In: Advanced Research in VLSI: Proc. of the 6th MIT Conf., pp. 133–138 (1990)Google Scholar