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Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

  • T. Murgan
  • M. Petrov
  • A. García Ortiz
  • R. Ludewig
  • P. Zipf
  • T. Hollstein
  • M. Glesner
  • B. Oelkrug
  • J. Brakensiek
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

With technology improvements, the main bottleneck in terms of performance, power consumption, and design reuse in single chip systems is proving to be generated by the on-chip communication architecture. Benefiting from the non-uniformity of the workload in various signal processing applications, several dynamic power management policies can be envisaged. Nevertheless, the integration of on-line power, performance and information-flow management strategies based on traffic monitoring in (dynamically) reconfigurable templates has yet to be explicitly tackled. The main objective of this work is to define the concept of run-time functional optimization of application specific standard products, and show the importance of integrating such techniques in reconfigurable platforms and especially their communication architectures.

Keywords

Interconnection Network Communication Architecture Dynamic Power Management Design Reuse Power Management Policy 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Benini, L., Bogliolo, A., De Micheli, G.: A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE Trans. on VLSI Systems 8(3), 299–316 (2000)CrossRefGoogle Scholar
  2. 2.
    Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. IEEE Computer, 70–78 (January 2002)Google Scholar
  3. 3.
    Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks. In: An Engineering Approach. Morgan Kaufmann Publishers, San Francisco (2003)Google Scholar
  4. 4.
    Hartenstein, R.: A Decade of Reconfigurable Computing: A Visionary Retrospective. In: Proc. of DATE, pp. 642–649 (2001)Google Scholar
  5. 5.
    Keutzer, K., Newton, A.R., Rabaey, J.M., Sangiovanni Vincentelli, A.: System- Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Trans. on CAD of Int. Circuits and Systems 19(12), 1523–1543 (2000)CrossRefGoogle Scholar
  6. 6.
    Murgan, T., García Ortiz, A., Petrov, M., Glesner, M.: A Stochastic Framework for Communication Architecture Evaluation in Networks-on-Chip. In: IEEE Intl. Symposium on Signals, Circuits and Systems (July 2003)Google Scholar
  7. 7.
    Seitz, C.: Let’s Route Packets Instead of Wires. In: Advanced Research in VLSI: Proc. of the 6th MIT Conf., pp. 133–138 (1990)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • T. Murgan
    • 1
  • M. Petrov
    • 1
  • A. García Ortiz
    • 1
  • R. Ludewig
    • 1
  • P. Zipf
    • 1
  • T. Hollstein
    • 1
  • M. Glesner
    • 1
  • B. Oelkrug
    • 1
  • J. Brakensiek
    • 2
  1. 1.Institute of Microelectronic SystemsDarmstadt University of TechnologyGermany
  2. 2.Nokia Research CenterBochumGermany

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