Very High Speed 17 Gbps SHACAL Encryption Architecture

  • Máire McLoone
  • J. V. McCanny
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


Very high speed and low area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and it is based on the SHA-1 hash algorithm. To date, there have been no performance metrics published on hardware implementations of this algorithm. A fully pipelined SHACAL-1 encryption architecture is described in this paper and when implemented on a Virtex-II X2V4000 FPGA device, it runs at a throughput of 17 Gbps. A fully pipelined decryption architecture achieves a speed of 13 Gbps when implemented on the same device. In addition, iterative architectures of the algorithm are presented. The SHACAL-1 decryption algorithm is derived and also presented in this paper, since it was not provided in the submission to NESSIE.




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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Máire McLoone
    • 1
  • J. V. McCanny
    • 1
  1. 1.DsiPTM Laboratories, School of Electrical and Electronic EngineeringThe Queen’s University of BelfastBelfastNorthern Ireland

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