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FPGA Based High Density Spiking Neural Network Array

  • Juan M. Xicotencatl
  • Miguel Arias-Estrada
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Pulsed neural networks can be applied to the design of dense arrays using minimum hardware resources in the interconnection among neurons. Using statistical saturation in pulse frequency coded neurons, a minimum size hardware neuron can be implemented. The proposed neuron is compact enough to be included in large arrays. The presented architecture has additional interesting characteristics like unrestricted topology and scalability. In this paper, the design and implementation of a high density spiking neural array is presented.

Keywords

Instantaneous Frequency External Memory Dense Array Spike Neural Network Pulse Frequency Modulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Schoenauer, T., Atasoy, S., Mehrtash, N., Klar, H.: Simulation of a Digital Neuro-Chip for Spiking Neural Networks. In: International Joint Conference on Neural Networks (IJCNN), Como, Italy (July 2000)Google Scholar
  2. 2.
    Schaefer, M., Schoenauer, T., Wolff, C., Hartmann, G., Klar, H., Rueckert, U.: Simulation of Spiking Neural Networks - Architectures and Implementations, Neurocomputing. Elsevier, Amsterdam (2001)zbMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Juan M. Xicotencatl
    • 1
  • Miguel Arias-Estrada
    • 1
  1. 1.Computer Science DepartmentINAOEMexico

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