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FPGA Implementation of Multi-layer Perceptrons for Speech Recognition

  • E. M. Ortigosa
  • P. M. Ortigosa
  • A. Cañas
  • E. Ros
  • R. Agís
  • J. Ortega
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this work we present different hardware implementations of a multi-layer perceptron for speech recognition. The designs have been defined using two different abstraction levels: register transfer level (VHDL) and a higher algorithmic-like level (Handel-C). The implementations have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. A study of the two considered approaches costs (silicon area), speed and required computational resources is presented.

Keywords

Speech Recognition Parallel Version High Level Description FPGA Implementation Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Widrow, B., Lehr, M.: 30 years of adaptive neural networks: Perceptron, Madaline and Backpropagation. Proceedings of the IEEE 78(9), 1415–1442 (1990)CrossRefGoogle Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • E. M. Ortigosa
    • 1
  • P. M. Ortigosa
    • 2
  • A. Cañas
    • 1
  • E. Ros
    • 1
  • R. Agís
    • 1
  • J. Ortega
    • 1
  1. 1.Dept. of Computer Architecture and Technology ETS Ingeniería InformáticaUniversity of GranadaGranadaSpain
  2. 2.Dept. of Computer Architecture and ElectronicsUniversity of AlmeríaAlmeríaSpain

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