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Testable Clock Routing Architecture for Field Programmable Gate Arrays

  • L. Kalyan Kumar
  • Amol J. Mupid
  • Aditya S. Ramani
  • V. Kamakoti
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The H-tree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex Logic Blocks, to detect and locate faults in the clock lines is proposed

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References

  1. 1.
    Mitra, S., Shirvani, P.P., McCluskey, J. E.: Fault Location in FPGA Based Reconfigurable Systems, BMDO/IST (1999)Google Scholar
  2. 2.
    Ullman, D. J.: Computational aspects of VLSI Design. Computer Science Press, Rockville, p. 84 Google Scholar
  3. 3.
    Lakamraju, V., Tessier, R.: Tolerating Operational Faults in Cluster-based FPGAs. In: FPGA 2000, Monterey, CA, USA (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • L. Kalyan Kumar
    • 1
  • Amol J. Mupid
    • 1
  • Aditya S. Ramani
    • 1
  • V. Kamakoti
    • 1
  1. 1.Department of Computer Science and EngineeringIndian Institute of Technology MadrasChennai, TamilnaduIndia

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