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Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology

  • Sanjay VidhyadharanEmail author
  • Ramakant
  • Gangishetty Akhilesh
  • Vaibhav Gupta
  • Anand Ravi
  • Surya Shankar Dan
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 215)

Abstract

This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art industry-standard 45 nm CMOS technology. Novel TFET structures have been proposed whose ON current (\( I_{\text{on}} \)) matches with that of the MOSFETs, while maintaining the OFF current (\( I_{\text{off}} \)) at least 3 orders of magnitude lower than the MOSFETs with the same width and at the same technology node. The key performance metrics of the optimised TFET-based circuits have been benchmarked with similar CMOS-based standard digital circuits like the simple inverter, 2 input NAND gate, 2 input NOR gate, 2 input XOR gate, 6 transistor SRAM and 3 stage inverter chain. The overall improvement in Power Delay Product (PDP) of the TFET-based circuits has been demonstrated to be more than 97% lesser than the corresponding CMOS circuits.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Sanjay Vidhyadharan
    • 1
    Email author
  • Ramakant
    • 1
  • Gangishetty Akhilesh
    • 1
  • Vaibhav Gupta
    • 1
  • Anand Ravi
    • 1
  • Surya Shankar Dan
    • 1
  1. 1.Department of Electrical & Electronics EngineeringBirla Institute of Technology & Science-PilaniHyderabadIndia

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