Sensing in Ferroelectric Memories and Flip-Flops

  • Ahmedullah Aziz
  • Sandeep Krishna Thirumala
  • Danni Wang
  • Sumitha George
  • Xueqing Li
  • Suman Datta
  • Vijaykrishnan Narayanan
  • Sumeet Kumar GuptaEmail author


Ferroelectric (FE) materials, by virtue of their polarization retention in the absence of the electric field, offer a unique method to introduce non-volatility in memories and logic. The exploration of FE materials in context of their application in compute and storage has been carried out in two forms: (1) as capacitors, in which the FE material is sandwiched between two metal layers and (2) in ferroelectric transistors (FEFETs), in which, FE is integrated into the gate stack of FETs. Both the devices have been explored to design non-volatile memories and flip-flops. The commonality between the two technologies is that they use remnant polarization in the FE to define the binary logic states. However, the sensing as well as the switching of the polarization requires considerably different techniques for FE capacitors and transistors. Moreover, the requirements of the application (memory, flip-flop, etc.) also dictate the methodology for reading or writing the logic state. This chapter discusses the device–circuit aspects of FE capacitors and FEFETs in the context of non-volatile memory and logic design, with a focus on the sensing techniques. We present a comparative description of the two technologies, highlighting the pros and cons of each and how different device structures yield significantly different sensing strategy.


Ferroelectric capacitors Ferroelectric transistors FERAM Flip-flop Non-volatile memories Non-volatile logic Polarization Reference generator Sense margin Restore 



The authors thank the DARPA Young Faculty Award program and  SRC-GRC for their support for the work on FEFET-based designs.


  1. 1.
    Park SP, Gupta S, Mojumder N, Raghunathan A, Roy K (2012) Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture”, In: Proceedings of the 49th annual design automation conference (DAC ’12). ACM, New York, NY, USA, pp 492–497.
  2. 2.
    Liu Y, Li Z, Li H, Wang Y, Li X, Ma K, Li S, Chang M-F, John S, Xie Y, Shu J, Yang H (2015) Ambient energy harvesting nonvolatile processors: from circuit to system. In: Proceedings of the 52nd annual design automation conference (DAC ’15). ACM, New York, NY, USA, Article 150, 6 p.
  3. 3.
    Henzler Stephan, Georgakos Georg, Eireiner Matthias, Nirschl Thomas, Pacha Christian, Berthold Joerg, Schmitt-Landsiedel Doris (2006) Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. IEEE J Solid-State Circ 41(7):1654–1661. Scholar
  4. 4.
    Ma K, Zheng Y, Li S, Swaminathan K, Li X, Liu Y, Sampson J, Xie Y, Narayanan V (2015) Architecture exploration for ambient energy harvesting nonvolatile processors. In: 2015 IEEE 21st international symposium on high performance computer architecture (HPCA), Burlingame, CA, 2015, pp 526–537.
  5. 5.
    Fackenthal R, Kitagawa M, Otsuka W, Prall K, Mills D, Tsutsui K, Javanifard J, Tedrow K, Tsushima T, Shibahara Y, Hush G (2014) A 16 Gb ReRAM with 200 MB/s write and 1 GB/s read in 27 nm technology. In: 2014 IEEE international solid-state circuits conference digest of technical papers (ISSCC), San Francisco, CA, 2014, pp 338–339.
  6. 6.
    Dong X, Muralimanohar N, Jouppi N, Kaufmann R, Xie Y (2009) Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. In: Proceedings of the conference on high performance computing networking, storage and analysis, Portland, OR, 2009, pp 1–12.
  7. 7.
    Lin CJ, Kang SH, Wang YJ, Lee K, Zhu X, Chen WC, Li X, Hsu WN, Kao YC, Liu MT, Chen WC, Lin YC, Nowak M, Yu N, Tran L (2009) 45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell. In: 2009 IEEE international electron devices meeting (IEDM), Baltimore, MD, 2009, pp 1–4Google Scholar
  8. 8.
    Zwerg M, Baumann A, Kuhn R, Arnold M, Nerlich R, Herzog M, Ledwa R, Sichert C, Rzehak V, Thanigai P, Eversmann BO (2011) An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications. In: 2011 IEEE international solid-state circuits conference, San Francisco, CA, 2011, pp 334–336Google Scholar
  9. 9.
    Endoh T, Koike H, Ikeda S, Hanyu T, Ohno H (2016) An overview of nonvolatile emerging memories—spintronics for working memories. IEEE J Emerg Select Top Circuits Syst 6(2):109–119CrossRefGoogle Scholar
  10. 10.
    Chun KC, Zhao H, Harms JD, Kim TH, Wang JP, Kim CH (2013) A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory. IEEE J Solid-State Circuits 48(2):598–610. Scholar
  11. 11.
    Govoreanu B, Kar GS, Chen YY, Paraschiv V, Kubicek S, Fantini A, Radu IP, Goux L, Clima S, Degraeve R, Jossart N, Richard O, Vandeweyer T, Seo K, Hendrickx P, Pourtois G, Bender H, Altimime L, Wouters DJ, Kittl JA, Jurczak M (2011) 10×10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. In: 2011 international electron devices meeting, Washington, DC, 2011, pp 31.6.1–31.6.4.
  12. 12.
    Boniardi M, Redaelli A, Cupeta C, Pellizzer F, Crespi L, D’Arrigo G, Lacaita AL, Servalli G (2014) Optimization metrics for phase change memory (PCM) cell architectures. In: 2014 IEEE international electron devices meeting, San Francisco, CA, 2014, pp 29.1.1–29.1.4.
  13. 13.
    Kohlstedt H, Mustafa Y, Gerber A, Petraru A, Fitsilis M, Meyer R, Böttger U, Waser R (2005) Current status and challenges of ferroelectric memory devices. Microelectron Eng 80, 1 (June 2005), 296–304.
  14. 14.
    Mojumder NN, Gupta SK, Choday SH, Nikonov DE, Roy K (2011) A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications. IEEE Trans Electron Devices 58(5):1508–1516. Scholar
  15. 15.
    Kawahara Akifumi, Azuma Ryotaro, Ikeda Yuuichirou, Kawai Ken, Katoh Yoshikazu, Hayakawa Yukio, Tsuji Kiyotaka, Yoneda Shinichi, Himeno Atsushi, Shimakawa Kazuhiko, Takagi Takeshi, Mikawa Takumi, Aono Kunitoshi (2013) An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput. IEEE J Solid-State Circuits 48(1):178–185. Scholar
  16. 16.
    Xie Y (2011) Modeling, architecture, and applications for emerging memory technologies. In: IEEE design & test of computers, vol 28, no 1, pp 44–51, Jan–Feb 2011.
  17. 17.
    Hoya K, Takashima D, Shiratake S, Ogiwara R, Miyakawa T, Shiga H, Doumae SM, Ohtsuki S, Kumura Y, Shuto S, Ozaki T, Yamakawa K, Kunishima I, Nitayama, Fujii S (2010) A 64-Mb chain FeRAM with quad BL architecture and 200 MB/s burst mode. In: IEEE transactions on very large scale integration (VLSI) systems, vol 18, no 12, pp 1745–1752, Dec 2010.
  18. 18.
    Aziz A, Shukla N, Datta S, Gupta SK (2015) COAST: correlated material assisted STT MRAMs for optimized read operation. In: 2015 IEEE/ACM international symposium on low power electronics and design (ISLPED), Rome, 2015, pp 1–6.
  19. 19.
    Lee YH, Kim HJ, Moon T, Do Kim K, Hyun SD, Park HW, Lee YB, Park MH, Hwang CS (2017) Preparation and characterization of ferroelectric Hf0·5Zr0·5O2 thin films grown by reactive sputtering. Nanotechnology 28:305703 (13 pp)Google Scholar
  20. 20.
    Lee1 MH, Chen P-G, Liu C, Chu K-Y, Cheng C-C, Xie M-J, Liu S-N, Lee J-W, Huang S-J, Liao M-H, Tang M, Li K-S, Chen M-C (2015) Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98 nm, SSfor=42 mV/dec, SSrev=28 mV/dec, switch-off <0.2 V, and hysteresis-free strategies. In: 2015 IEEE international electron devices meeting (IEDM), Washington, DC, 2015, pp 22.5.1–22.5.4.
  21. 21.
    Lee M-H, Chen P-G, Liu C, Chu K-Y, Cheng C-C, Xie M-J, Liu S-N, Lee J-W, Huang S-J, Liao M-H, Tang M, Li K-S, Chen M-C (2015) Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98 nm, SSfor=42 mV/dec, SSrev=28 mV/dec, switch-OFF <0.2 V, and hysteresis-free strategies. In: IEEE international electron devices meeting (IEDM), Dec 2015Google Scholar
  22. 22.
    Chanthbouala André, Crassous Arnaud, Garcia Vincent, Bouzehouane Karim, Fusil Stéphane, Moya Xavier, Allibe Julie, Dlubak Bruno, Grollier Julie, Xavier Stéphane, Deranlot Cyrile, Moshar Amir, Proksch Roger, Mathur Neil D, Bibes Manuel, Barthélémy Agnès (2012) Solid-state memories based on ferroelectric tunnel junctions. Nat Nanotechnol 7:101–104. Scholar
  23. 23.
    Wang D, George S, Aziz A, Datta S, Narayanan V, Gupta SK (2016) Ferroelectric transistor based non-volatile flip-flop. In: Proceedings of the 2016 international symposium on low power electronics and design (ISLPED ’16). ACM, New York, NY, USA, 10–15,
  24. 24.
    Shiga H et al (2010) A 1.6 GB/s DDR2 128 Mb chain FeRAM with scalable octal bitline and sensing schemes. IEEE J Solid-State Circuits 45(1):142–152. Scholar
  25. 25.
    Sheikholeslami A, Gulak PG (2000) A survey of circuit innovations in ferroelectric random-access memories. Proc IEEE 88(5):667–689. Scholar
  26. 26.
    Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8(2):405–410CrossRefGoogle Scholar
  27. 27.
    Eslami Y, Sheikholeslami A, Masui S, Endo T, Kawashima S (2002) A differential-capacitance read scheme for FeRAMs. In: 2002 symposium on VLSI circuits. Digest of technical papers (Cat. No. 02CH37302), Honolulu, HI, USA, 2002, pp 298–301.
  28. 28.
    Eslami Y, Sheikholeslami A, Masui S, Endo T, Kawashima S (2004) Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). IEEE J Solid-State Circuits 39(11):2024–2031. Scholar
  29. 29.
    Takashima D, Kunishima I (1998) High-density chain ferroelectric random access memory (chain FRAM). IEEE J Solid-State Circuits 33:787–792CrossRefGoogle Scholar
  30. 30.
    George S, Ma K, Aziz A, Li X, Khan A, Salahuddin S, Chang M-F, Datta S, Sampson J, Gupta S, Narayanan V (2016) Nonvolatile memory design based on ferroelectric FETs. In: Proceedings of the 53rd annual design automation conference (DAC ’16). ACM, New York, NY, USA, Article 118, 6 p, 2016.
  31. 31.
    Gupta SK et al (2017) Harnessing ferroelectrics for non-volatile memories and logic. In: 2017 18th international symposium on quality electronic design (ISQED), Santa Clara, CA, 2017, pp 29–34.
  32. 32.
    Wang J, Liu Y, Yang H, Wang H (2010) A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications. In: The 2010 international conference on green circuits and systems, Shanghai, 2010, pp 646–650.
  33. 33.
    Kimura H et al (2013) Highly reliable non-volatile logic circuit technology and its application. Int Symp Mult-Valued Logic 212–218Google Scholar
  34. 34.
    Qazi M, Amerasekera A, Chandrakasan AP (2014) A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-μm CMOS for nonvolatile processing in digital systems. IEEE J Solid-State Circuits 49(1):202–211. Scholar
  35. 35.
    Li X et al (2017) Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops. IEEE Trans Circuits Syst I Regul Pap 64(11):2907–2919. Scholar
  36. 36.
    Benedetto JM, Roush ML, Lloyd IK, Ramesh R (1994) Imprint of ferroelectric PLZT thin-film capacitors with lanthanum strontium cobalt oxide electrodes. In: Proceedings of the 9th international symposium on application of ferroelectrics, pp 66–69Google Scholar
  37. 37.
    Moazzami R, Abt N, Nissan-Cohen Y, Shepherd WH, Brassington MP, Hu C (1991) Impact of polarization relaxation on ferroelectric memory performance. In: Digest of technical papers. 2005 symposium on VLSI circuits, May 1991, pp 61–62Google Scholar
  38. 38.
    Sumi T, Moriwaki N, Nakane G, Nakakuma T, Judai Y, Uemoto Y, Nagano Y, Hayashi S, Azuma M, Fujii E, Katsu S, Otsuki T, McMillan L, de Araujo CP, Kano G (1994) A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns. In: ISSCC Digest of Technical Papers, pp 268–269Google Scholar
  39. 39.
    McAdams HP et al (2004) A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process. IEEE J Solid-State Circuits 39(4):667–677. Scholar
  40. 40.
    Miyakawa T, Tanaka S, Itoh Y, Takeuchi Y, Ogiwara R, Doumae AM, Takenaka H, Kunishima I, Shuto S, Hidaka O, Ohtsuki S, and Tanaka S (1999) A 0.5 m 3 V 1T1C 1 Mbit FRAM with a variable reference bitline voltage scheme via a fatigue free reference capacitor. In: ISSCC digest of technical papers, pp 104–105Google Scholar
  41. 41.
    Lowrey TA, Kinney WL (1996) Folded bit line ferroelectric memory device. U.S. Patent 5 541 872, 30 July 1996Google Scholar
  42. 42.
    Wilson DR, Meadows HB (1996) Voltage reference for a ferroelectric 1T/1C based memory. U.S. Patent 5 572 459, Nov 5Google Scholar
  43. 43.
    Papaliolios AG (1993) Dynamic adjusting reference voltage for ferroelectric circuits. U.S. Patent 5 218:566, 8 June 1993Google Scholar
  44. 44.
    Ze Jia, Zhongren Zou, Tianling Ren, Hongyi Chen (2010) An asymmetrical sensing scheme for 1T1C FRAM to increase the sense margin. J. Semicond. 31:115001CrossRefGoogle Scholar
  45. 45.
    Jia Z, Zhang G, Liu J, Liu Z, Liou JJ (2014) Reference voltage generation scheme enhancing speed and reliability for 1T1C-type FRAM. Electron Lett 50(3):154–156. Scholar
  46. 46.
    Kawashima S, Endo T, Yamamoto A, Nakabayashi K, Nakazawa M, Morita K, Aoki M (2002) Bitline GND sensing technique for low-voltage operation FeRAM. IEEE J Solid-State Circuits 37(5):592–598, May 2002.
  47. 47.
    Jia Z, Zhang G, Zhang MM, Ren T, Chen H (2010) A novel fatigue-insensitive self-referenced scheme for 1T1C FRAM. In: 2010 IEEE international memory workshop, Seoul, 2010, pp 1–2.
  48. 48.
    Chandler T, Sheikholeslami A, Masui S, Oura M (2003) An adaptive reference generation scheme for 1T1C FeRAMs. In: 2003 symposium on VLSI circuits. Digest of technical papers (IEEE Cat. No.03CH37408), Kyoto, Japan, 2003, pp 173–174.
  49. 49.
    Conte A, Giudice GL, Palumbo G, Signorello A (2005) A high-performance very low-voltage current sense amplifier for nonvolatile memories. IEEE J Solid-State Circuits 40(2):507–514. Scholar
  50. 50.
    Schinkel D, Mensink E, Klumperink E, van Tuijl E, Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold Time. In: 2007 IEEE international solid-state circuits conference. Digest of technical papers, San Francisco, CA, 2007, pp 314–605.

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Ahmedullah Aziz
    • 1
  • Sandeep Krishna Thirumala
    • 1
  • Danni Wang
    • 2
  • Sumitha George
    • 2
  • Xueqing Li
    • 2
  • Suman Datta
    • 3
  • Vijaykrishnan Narayanan
    • 2
  • Sumeet Kumar Gupta
    • 1
    • 2
    Email author
  1. 1.School of Electrical and Computer EngineeringPurdue UniversityWest LafayetteUSA
  2. 2.School of Electrical Engineering and Computer SciencePennsylvania State UniversityState CollegeUSA
  3. 3.Department of Electrical EngineeringUniversity of Notre DameSouth BendUSA

Personalised recommendations