Experimental Tests of the Landauer Principle in Electron Circuits, and Quasi-Adiabatic Computing Systems

  • Alexei O. Orlov
  • Ismo K. Hänninen
  • César O. Campos-Aguillón
  • Rene Celis-Cordova
  • Michael S. McConnell
  • Gergo P. Szakmany
  • Cameron C. Thorpe
  • Brian T. Appleton
  • Graham P. Boechler
  • Craig S. Lent
  • Gregory L. Snider


Power dissipation is one of the most important factors limiting the development of integrated circuits. In this chapter, we will explore the limits of energy dissipation in computation with experiments and circuit designs. Our experiments show that there is no fundamental limit on energy that must be dissipated to perform computation as long as information is preserved, in agreement with the Landauer principle. The erasure of information leads to a loss of bit energy with an ultimate lower limit of kBT ln2, sometimes incorrectly referred to as the “Landauer limit for energy dissipation in computation.” We present an experiment where a dissipation of 0.005 kBT which is far below the limit of kBT ln2 occurs in reversible adiabatic bit manipulation, and experimentally demonstrate that dissipation of the full bit energy occurs if information is erased. To exploit the advantages of quasi-adiabatic reversible computation, we discuss adiabatic logic systems, and present the design of a microprocessor based upon adiabatic logic. Due to their inherent leakage current, field-effect transistors have limitations in adiabatic implementations. We discuss possible devices that have a better match to adiabatic systems. Finally, we present experiments making direct measurement of the heat generated in logical operations.


Low power logic Landauer principle Adiabatic circuits Adiabatic microprocessor Reversible logic Experimental demonstration of the Landauer principle Design tools for adiabatic circuits Thermal measurements Nanothermocouples Bennett clocking Retractile cascade Energy in computation Energy-delay-area metric Low-noise measurements Quantum-dot cellular automata Adiabatic capacitive logic Ultimate shannon limit CMOS power dissipation Micromechanical logic Nano-relay logic Split-rail charge recovery logic Differential thermometry 



This work was supported in part by the DoD, Air Force Office of Scientific Research, National Defense Science and Engineering Graduate (NDSEG) Fellowship, 32 CFR 168a, and the National Science Foundation under Grants ECCS09-01659, ECCS09-01659, DGE-1313583, and ECCS-1509087. The authors are also grateful to Amy L. Snider for assistance in preparation of this chapter.


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Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Alexei O. Orlov
    • 1
  • Ismo K. Hänninen
    • 1
  • César O. Campos-Aguillón
    • 1
  • Rene Celis-Cordova
    • 1
  • Michael S. McConnell
    • 1
  • Gergo P. Szakmany
    • 1
  • Cameron C. Thorpe
    • 1
  • Brian T. Appleton
    • 1
  • Graham P. Boechler
    • 1
  • Craig S. Lent
    • 1
  • Gregory L. Snider
    • 1
  1. 1.Department of Electrical EngineeringUniversity of Notre DameNotre DameUSA

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