Programmable Architectures for Histogram of Oriented Gradients Processing
There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of hand-crafted VHDL code.
This work has been undertaken in collaboration with Heriot-Watt University in a project funded by the Engineering and Physical Science Research Council (EPSRC) through the EP/K009583/1 grant. Colm Kelly has received support from Thales Air Defence.
- 2.Jain R, Kasturi R and Schunck B G (1995) Machine Vision. McGraw-Hill, Inc.Google Scholar
- 4.Xilinx Inc. (2016) System Generator for DSP. Available via http://www.xilinx.com. Cited 29 April 2017.
- 5.MathWorks (2016) HDL Coder. Available via http://uk.mathworks.com/products/hdl-coder/index.html. Cited 29 April 2017.
- 6.McKinsey and Company (2012) McKinsey on Semiconductors. Available via http://www.mckinsey.com. Cited 29 April 2017.
- 7.Xilinx Inc. (2015) DS183: Viretx-7 and XT FPGAs Data Sheet: DC and AC Switching Characteristics. Available via http://www.xilinx.com. Cited 29 April 2017.
- 8.ARM Ltd. ARM7TDMI Technical Reference Manual (ARM DDI 0029G). Available via http://www.atmel.com. Cited 29 April 2017.
- 9.Xilinx Inc. (2011) LogiCORE IP Divider Generator v3.0. Available via http://www.xilinx.com. Cited 29 April 2017.
- 10.Texas Instruments (2010) TMS3206678 Rev.E. Available via http://www.ti.com. Cited 29 April 2017.
- 11.Eker J and Janneck J (2003) CAL language report. University of California at Berkeley Technical Report UCB/ERL M, (3).Google Scholar
- 15.Macii E, Paliouras V and Koufopavlou O (2004) Power Aware Dividers in FPGA. Proc. of Power and Timing Modeling, Optimization and Simulation, 574–584.Google Scholar
- 16.Thomas D B, Howes L and Luk W (2009) A Comparison of CPUs, GPUs, FPGAs, and Massively Parallel Processor Arrays for Random Number Generation. Proc. of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 63–72.Google Scholar
- 17.Dalal N and Triggs B (2005) Histograms of oriented gradients for human detection. Proc. of IEEE Conference on Computer Vision and Pattern Recognition, 886–893.Google Scholar
- 18.Hahnle M, Saxen F, Hisung M, Brunsmann U and Doll K (2013) FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images. Proc. of IEEE Conference on Computer Vision and Pattern Recognition, 629–635.Google Scholar
- 19.Bauer S, Brunsmann U and Schlotterbeck-Macht S (2009) FPGA Implementation of a HOG-based Pedestrian Recognition System. Proc. of IMPC-Workshop, Karlsruhe.Google Scholar
- 20.Xie S, Li Y, Jia Z and Ju L (2013) Binarization based implementation for real-time human detection. Proc. of International Conference on Field-Programmable Technology, 1–4.Google Scholar
- 21.Kadota R, Sugano H, Hiromoto M, Ochi H, Miyamoto R and Nakamura Y (2009) Hardware Architecture for HOG Feature Extraction. Proc. of International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 1330–1333.Google Scholar
- 22.Siddiqui F M, Russell M, Bardak B, Woods R and Rafferty K (2014) IPPro: FPGA based image processing processor. Proc. of IEEE Workshop on Signal Processing Systems, 1–6.Google Scholar
- 23.Kelly C, Siddiqui F M, Bardak B and Woods R (2014) Histogram of oriented gradients front end processing: an FPGA based processor approach. Proc. of IEEE Workshop on Signal Processing Systems, 1–6.Google Scholar
- 24.Negi K, Dohi K, Shibata Y and Oguri K (2011) Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. Proc. of International Conference on Field-Programmable Technology, 1–8.Google Scholar