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Programmable Architectures for Histogram of Oriented Gradients Processing

  • Colm Kelly
  • Roger Woods
  • Moslem Amiri
  • Fahad Siddiqui
  • Karen Rafferty
Chapter

Abstract

There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of hand-crafted VHDL code.

Notes

Acknowledgements

This work has been undertaken in collaboration with Heriot-Watt University in a project funded by the Engineering and Physical Science Research Council (EPSRC) through the EP/K009583/1 grant. Colm Kelly has received support from Thales Air Defence.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Colm Kelly
    • 1
  • Roger Woods
    • 2
  • Moslem Amiri
    • 3
  • Fahad Siddiqui
    • 2
  • Karen Rafferty
    • 2
  1. 1.Thales Air DefenceBelfastUK
  2. 2.Queen’s University of BelfastBelfastUK
  3. 3.University of BristolBristolUK

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