MASH Sigma-Delta Modulators
So far only the possibility of creating stable, high-order Sigma-Delta modulators through a careful loop architecture choice and/or using multi-bit quantization has been considered. As demonstrated in previous chapters, although this approach can yield effective high-order loop designs, it also results in mathematically intensive (the Schreier’s Toolbox helps considerably in this regard!) and extensive simulations that are required to check that instability does not occur for any envisioned modulator input. Moreover, especially for low oversampling values, it is almost impossible to obtain high SQNR performances in a single-bit quantizer modulator simply by increasing the order of the loop filter since stability considerations limit the permissible input signal amplitude for higher-order loops, which counteracts the improved noise suppress. On this regard, multi-bit quantizers allow, to some extent, to overcome such limitations but at the cost of increased complexity to ensure in-band linearity of the internal DAC, typically limiting the practical application to 4–5 bits at the most.
- 1.Schreier R, Temes GC. Understanding delta-sigma data converters. Hoboken: Wiley; 2005.Google Scholar
- 5.Geerts Y, Steyaert M, Sansen W. Design of multibit delta sigma A/D converters. New York: Kluwer Academic Publisher; 2002.Google Scholar
- 6.Reiss JD. Understanding sigma-delta modulation: the solved and unsolved isses. JAES. 2008;56(1/2):49–64.Google Scholar
- 10.Graells SF. Integrated heterogeneous systems design. [Online] http://www.cnm.es/~pserra/uab/ihsd/ihsd-5-dsm.pdf. Date accessed 24 June 2017.