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Nanopackaging pp 921-956 | Cite as

Flip-Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities

  • Debendra Mallik
  • Ravi MahajanEmail author
  • Nachiket Raravikar
  • Kaladhar Radhakrishnan
  • Kemal Aygun
  • Bob Sankman
Chapter

Abstract

Semiconductor devices reached the nanoscale in the 2000s and have continued to shrink their features in accordance with Moore’s law. Semiconductor packaging, which is critical to ensure connectivity of these fine-featured semiconductor devices, has also kept pace with Moore’s law scaling to enable products to take advantage of the performance scaling opportunities afforded by silicon scaling. In doing so, packaging has been increasingly challenged to provide requisite interconnect scaling, form-factor scaling, process scaling, enhanced thermal management, improved signal integrity, improved power delivery, and adequate thermomechanical reliability in increasingly diverse applications. This chapter systematically examines the evolution, challenges, and opportunities of different aspects of flip-chip package scaling, typically used for high-performance silicon. Materials continue to play a critical role in the evolution of flip-chip packaging, and their influence and impact are also discussed to highlight their contributions and importance.

Keywords

Moore’s law Transistor scaling Flip-chip packaging Package architectures Form-factor scaling Space transformation Interconnect classes Die-package interconnects Die-die interconnects Within-package interconnects Package-board interconnects Chip functionality Solder interconnects Alignment tolerances Interconnect pitch scaling Underfill process Capillary underfill Epoxy films Deflux Pre-dispensed underfill FLI joints C4 joints Bump melting temperatures Copper bumps Assembly process Coplanarity Joint sizes Bump pitch Electromigration Current density Thermomechanical stresses Low-l dielectrics Chip compliance Embedded multi-die interconnect bridge (EMIB) Silicon interposer Through-silicon vias (TSVs) Multi-chip packaging (MCP) Plated through holes (PTH) Buildup layers Micro-vias Semi-additive process (SAP) Solder volume Pin grid array (PGA) Land grid array (LGA) Ball grid array (BGA) Power consumption Voltage rails Transient noise Multi-core processors Power supply Power management Power rails Voltage regulators Fully integrated voltage regulator (FIVR) Motherboard VR (MBVR) Power delivery network (PDN) Power FETs Switching regulator Inductors Signal integrity Bandwidth demand Package signal integrity (SI) Insertion loss Return loss Cross-talk Single-ended signaling Differential signaling IO interfaces IO density Half-line pitch Thermal design power (TDP) Junction temperature Thermal resistance Temperature differential Thermal power density Nonuniform power distribution Hot spots Thermal interface materials (TIM) Contact resistance Integrated heat spreader (IHS) Bond-line thickness (BLT) Thermoelectric devices Peltier devices Conductance Coefficient of thermal expansion (CTE) Thermomechanical stresses RC delay Carbon nanotubes (CNT) Structural integrity Nanoparticle dispersion Nanocomposites Rule of mixtures Package warpage Modulus Toughness Defects Bell’s law Miniaturization Battery life Wafer-level packages Wafer-level chip-scale packages (WLCSP) fan-out wafer-level packaging (FO-WLP) Redistribution layer (RDL) Reconstituted wafers System in package (SiP) Package on package (POP) Process yield loss 

Acronyms

BGA

Ball Grid Array

BOM

Bill of Materials

BPA

Bisphenol-A

BW

Bandwidth

C4

Controlled Collapse Chip Connection

CG

Coarse-grained

CNT

Carbon Nanotube

CPI

Chip Package Interactions

CPU

Central Processing Unit

CSAM

C-Mode (Confocal) Scanning Acoustic Microscopy

CSP

Chip Scale Package

CTE

Coefficient of Thermal Expansion

CVFF

Consistent Valence Force Field

DEM

Discrete Element Model

DFT

Density Functional Theory

DIP

Dual Inline Package

DPD

Dissipative Particle Dynamics

DRAM

Dynamic Random Access Memory

EM

Electromagnetic

EMC

Epoxy Molding Compound

EMIB

Embedded Multi-Die Interconnect Bridge

EPN

Epoxy Phenol Novolac

FCBGA

Flip Chip Ball Grid Array

FCC

Face-centered cubic

FCIP

Flip Chip in Package

FCLGA

Flip Chip Land Grid Array

FCPGA

Flip Chip Pin Grid Array

FET

Field Effect Transistor

FIVR

Fully Integrated Voltage Regulator

FLI

First Level Interconnect

FOPLP

Fan-Out Panel Level Package

FOWLP

Fan-Out Wafer Level Package

GPU

Graphics Processing Unit

HMC

Hybrid Memory Cube

HSIO

High Speed Input/Output

HVM

High Volume Manufacturing

IC

Integrated Circuit

IHS

Integrated Heat Spreader

ILD

Inner Layer Dielectric

I/O

Input/Output

IOT

Internet of Things

KGD

Known Good Die

LGA

Land Grid Array

LJ

Lennard-Jones

LQFP

Low-profile Quad Flat Package

MBVR

Mother Board Voltage Regulator

MCP

Multi-Chip Package

MD

molecular dynamics

MM

molecular mechanics

MMAP

Molded Matrix Array Package

MOSFET

Metal-Oxide-Semiconductor FET

NEMD

Non-Equilibrium Molecular Dynamics

NPU

Network Processing Unit

NPT

Isothermal-isobaric ensemble (conservation of substance amount N, pressure P and temperature T)

NVT

canonical ensemble (conservation of substance amount N, volume V and temperature T)

PBC

Periodic Boundary Conditions

PBGA

Plastic Ball GA

PCB

Printed Circuit Board

PCFF

Polymer Consistent Force Field

PDN

Power Delivery Network

PGA

Pin Grid Array

PoP

Package on Package

PTH

Plated Through Hole

QFJ

Quad Flat J-Leaded Package

QFN

Quad Flat Package No Lead

QFP

Quad Flat Package

RC

Resistance x Capacitance (time constant)

RDL

Redistribution Layer

RF

Radio Frequency

RH

Relative Humidity

RT

Room Temperature

SAC

Tin-Silver-Copper (Sn-Ag-Cu)

SAP

Semi-Additive Process

SCSP

Stacked die Chip Scale Package

SI

Signal Integrity

SiP

System in a Package

SLI

Second Level Interconnect

SoC

System on a Chip

SOJ

Small Outline J-Leaded Package

SOP

Small Outline Package

SRAM

Static Random Access Memory

SSOP

Shrink Small Outline Package

TCB

Thermo-Compression Bonding

TCP

Tape Carrier Package

TDP

Thermal Design Power

Tg

Glass Transition Temperature

TIM

Thermal Interface Material

TQFP

Thin Quad Flat Package

TSOP

Thin Small Outline Package

TSV

Through Silicon Via

UBM

Under Bump Metallization

VdW

Van der Waals

VHR

Voltage Holding Ratio

VR

Voltage Regulator

WLCSP

Wafer Level Chip Scale Package

WLP

Wafer Level Package

ZIP

Zig-Zag Inline Package

Notes

Acknowledgments

The authors would like to thank Brent Stone and Donald Tran from Intel Corporation for their help in providing background information on socket technologies. We would also like to thank Chris Matayabas and Gaurang Choksi for reviewing the chapter and providing guidance on enhancing the chapter.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Debendra Mallik
    • 1
  • Ravi Mahajan
    • 1
    Email author
  • Nachiket Raravikar
    • 2
  • Kaladhar Radhakrishnan
    • 1
  • Kemal Aygun
    • 1
  • Bob Sankman
    • 1
  1. 1.Intel CorporationChandlerUSA
  2. 2.Tectus CorporationSaratogaUSA

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