The production of an IC requires a translation of its specifications into a description of the layers from which it will be built. Usually, the patterns in all layers are represented in a layout. The generation of such a layout is usually done via an interactive graphics display for handcrafted layouts (certain analog circuits and/or some basic digital cells) or by means of synthesis, place-and-route and floor-planning tools, as discussed in Chap. 7. Figure 9.1 shows an example of a complex IC containing several functional blocks, many of which consist of a combination of handcrafted, synthesised and memory blocks.
- 26.Copied with permission from ASML from the following website: <www.asml.com/asmldotcom/show.do?ctx=10448&rid=10081>
- 27.Joe Kwan, “Sign-off lithography simulation and multi-patterning must play well together”, http://www.techdesignforums.com/practice/tag/multipatterning/, August 12, 2014
- 28.Ed Korczynski, “EUV Resists and Stochastic Processes”, Semiconductor Manufacturing & Design Community, http://semimd.com/blog/tag/euv/, March 4, 2016
- 29.Peter Singer, “Nanoimprint-Lithography-A-Contender-for-32-nm”, <www.ferret.com.au/n/Nanoimprint-Lithography-A-Contender-for-32-nm-n676715>
- 30.Peter Clarke, “Report: Toshiba adopts imprint litho for NAND production”, EE|Times (Analog), June 07, 2016Google Scholar