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Bits on Chips pp 233-250 | Cite as

Packaging

  • Harry Veendrick
Chapter

Abstract

The development of the IC package is a dynamic technology. Applications that were unattainable only a decade ago are now commonplace thanks to advances in package design. Moreover, the increasing demand for smaller, faster and cheaper products is forcing the packaging technology to keep pace with the progress in semiconductor technology.

References1

  1. 50.
    JEDEC, Joint Electron Devices Engineering Councils, <www.jedec.org>
  2. 51.
    OKI Semiconductor, “Package Information 5. Thermal-Resistance of IC Package”, <www.ti.com/lit/an/spra953c/spra953c.pdf>
  3. 52.
    G.Q. Zhang, et al., “Mechanics of Microelectronics”, Springer 2006, <www.springer.com>
  4. 53.
    Kevin J. Hess et al., “Reliability of Bond Over Active Pad Structures for 0.13-μm CMOS Technology”, <www.freescale.com/files/technology_manufacturing/doc/ECTC_2003_BOND_OVER_ACTIVE_KH.pdf>
  5. 54.
    Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM”, <www.elpida.com/en/news/2009/08-27.html>
  6. 55.
    Rao R. Tummala, “Moore's Law Meets Its Match”, IEEE Spectrum, June 2006, pp. 38–43, <http://spectrum.ieee.org/computing/hardware/moores-law-meets-its-match/0>

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Harry Veendrick
    • 1
  1. 1.HeezeThe Netherlands

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