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Bits on Chips pp 203-220 | Cite as

Testing and Yield

  • Harry Veendrick
Chapter

Abstract

An integrated circuit can fall victim to a large variety of failure mechanisms. Ideally, the related problems are detected early in the manufacturing process. However, some only show up during the final tests, or even worse, they might not be identified before the chip is soldered on a customer’s board.

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    Application note number 5: “Choosing a yield model with “11 Select a yield model or default”, <www.icknowledge.com/our_products/Applications%20note%20number%205.pdf>
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    L. Peters, “DFN: Worlds Collide, Then Cooperate”, Semiconductor International, June 2005, <www.synopsys.com/Tools/TCAD/CapsuleModule/semi_int_jun05.pdf>

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Harry Veendrick
    • 1
  1. 1.HeezeThe Netherlands

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