Models for Determining the Influence of DF

  • Vazgen Melikyan


A number of semiempirical models for determining the influence of various external (total radiation dose, ambient temperature, supply voltage, slope of the input signal, amplitude of the input signal, number of loads) and internal (interconnects, power buses) DFs on the parameters of models of logical elements for TTL, ECL and CMOS technologies are described.


  1. 1.
    Kang S., Leblebici Y., Kim Ch. CMOS Digital Integrated Circuits Analysis & Design. -McGraw-Hill Education; 4 edition, 2014. -736p.Google Scholar
  2. 2.
    Mehler R.W. Digital Integrated Circuit Design Using Verilog and Systemverilog. -Newnes; 1 edition, 2014. -448p.Google Scholar
  3. 33.
    Boylestad R., Nashelsky L. Electronic Devices and Circuit Theory. -Prentice Hall; 10 edition, 2008. -912p.Google Scholar
  4. 35.
    Jespers P., Murmann B. Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. -Cambridge University Press, 2017. -342p.Google Scholar
  5. 70.
    Flynn D., Aitken R., Gibbons A., Shi K. Low Power Methodology Manual: For System-on-Chip Design. -Springer, 2011. -320p.Google Scholar
  6. 72.
    Jean Walrand K.B., Zobrist G. Advanced Computer Performance Modeling and Simulation. -CRC Press, 1998. -356p.Google Scholar
  7. 78.
    Tsividis Y. Mixed Analog-Digital VLSI Devices and Technology. -Kluwer Academic Publishers, 2002. -300p.Google Scholar
  8. 80.
    Maniwa T. Focus Report: ASICs Today // Integrated System Design Magazine. -2000. -P. 93-95, 98.Google Scholar
  9. 32.
    Ashok B. Mehta. ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. -Springer, 2017. -328p.Google Scholar
  10. 38.
    Ott H.W.. Electromagnetic Compatibility Engineering. -Wiley; 1st edition, 2009. -872p.CrossRefGoogle Scholar
  11. 41.
    Cherniak M.E., Smolin A.A., Ulanova A.V., Nikiforov A.Y. Investigation of Nonuniform Degradation of CMOS-Sensor Light-Sensitive Surface under Gamma-Irradiation // IEEE Radiation and Its Effects on Components and Systems (RADECS). -2015. -P. 1-3.Google Scholar
  12. 42.
    Agakhanyan T.M. Circuit-Design Techniques of Radiation Hardening for Monolithic Op Amps // Russian Microelectronics. -2004. -Vol. 33, No. 3. -P. 183-187.CrossRefGoogle Scholar
  13. 43.
    Cherniak M., Smolin A., Ulanova A. Investigation of Nonuniform Degradation of CMOS-Sensor Light-Sensitive Surface under Gamma-Irradiation // IEEE Radiation and Its Effects on Components and Systems (RADECS). -2015. -P. 1-3.Google Scholar
  14. 44.
    Artamonov A.S., Demidov A.A., Kalashnikov O.A., Nikiforov A.Y., Polevich S.A., Telets V.A. Technique and Results of ADC/DAC Radiation Hardness Simulation Tests//Third Workshop on Electronics for LHC Experiments. -London, 1997. -P. 410-414.Google Scholar
  15. 45.
    Kloukinas K. Development of a radiation tolerant 2.0V standard cell library using a commercial deep submicron technology for the LHC experiments // Fourth Workshop on Electronics for LHC Experiments. -Rome, 1998. -P. 574-580.Google Scholar
  16. 46.
    Lacoe R. Application of Hardness-By-Design Methodology to Radiation-Tolerant ASIC Technologies // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 2334-2341.Google Scholar
  17. 47.
    Agakhanyan T.M., Astvatsaturyan E.P., Skorobogatov P.K. Radiation effects in integrated microcircuits. -Ì.: Enerergoatomizdat, 1989. -256p. (in Russian)Google Scholar
  18. 48.
    Korshunov F.P., Bogatirev Yu V., Vavilov V.A. The effect of radiation on integrated microcircuits. -Minsk: Science and Technology, 1986. -254p. (in Russian)Google Scholar
  19. 49.
    Chumakov A.I., Egorov A.N., Mavritsky O.B., Yanenko A.V. Evaluation of Moderately Focused Laser Irradiation as a Method for Simulating Single-Event Effects // Russian Microelectronics. -2004. -Vol. 33, No. 2. -P. 106-110.Google Scholar
  20. 50.
    Barnaby H.J., Cirba C.R., Schrimpf R.D., Fleetwood D.M., Pease R.L., Shaneyfelt M.R., Turflinger T., Krieg J.F., Maher M.C. Origins of total dose response variability in linear bipolar microcircuits // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 2342-2349..Google Scholar
  21. 51.
    Faccio F. Total dose and SEU measurement of test structures in a deep submicron technology // Fourth Workshop on Electronics for LHC Experiments. -Rome, 1998. -P. 114-117.Google Scholar
  22. 52.
    Campbell M. A pixel readout chip for 10-30 Mrad in standard 0.25mm CMOS//IEEE Nature Sounds Society (NSS) Symposium. -Toronto, 1998. -P. 823-891.Google Scholar
  23. 53.
    Osborn J. Total Dose Hardness of Three Commercial CMOS Microelectronics Foundries // IEEE Transactions on Nuclear Science. -1998. -Vol. 45, No. 3. -P. 1458-1463.Google Scholar
  24. 54.
    Holmes-Siedle A., Adams L. Handbook of Radiation Effects. -Oxford University Press, 1993. -218p.Google Scholar
  25. 55.
    Snoeys W., Faccio F., Burns M. Layout Techniques to Enhance the Radiation Tolerance of Standard CMOS Technologies Demonstrated on a Pixel Readout Chip // Nuclear Instructions and Methods. -2000. -Vol. 439. -P. 349-360.Google Scholar
  26. 56.
    Knoll G.F. Radiation Detection and Measurement. -John Wiley & Sons, 2000. -194p.Google Scholar
  27. 57.
    Candelori A., Contarato D., Bacchetta N. High-Energy Ion Irradiation Effects on Thin Oxide p-Channel MOSFETs // IEEE Transactions on Nuclear Science. -2002. -Vol. 49, No. 3. -P. 1364-1371.Google Scholar
  28. 58.
    Melikyan V. Logic simulation of digital circuits exposed to radiation // Facta universitatis, series: Electronics and Energetics. -Nis, 1999. -Vol. 12, No. 1. -P. 1-16.Google Scholar
  29. 86.
    Goryachev V.A. Effect of Discontinuities on ULSI On-Chip Interconnection Characteristics // Russian Microelectronics. -2002. -Vol. 31, No. 5. -P. 326-334.Google Scholar
  30. 87.
    Hong X.L., Zhu Q., Jing T. Non-rectilinear on-chip interconnect-an efficient routing solution with high performance // Chinese Journal of Semiconductors. -2003. -Vol. 24, No. 3. -P. 225-233.Google Scholar
  31. 88.
    Xu J., Hong X., Jing T., Zhang L. ETEM: An Efficient Gate and Interconnect Timing Estimator Considering Cross-Coupling for High Performance Layout//IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 254-257.Google Scholar
  32. 89.
    Wang X., Yu W., Liu D., Wang Z. Fast extraction of 3-D interconnect resistance: numerical-analytical coupling method // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 315-318.Google Scholar
  33. 90.
    Li T., Wang Z. 2-D interconnect inductance and resistance extraction based on the coupled circuit method // Journal of Computer-Aided Design and Computer Graphics. -2003. -Vol. 15, No. 1. -P. 102-106.Google Scholar
  34. 91.
    Wu B. High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging // IEEE Semiconductor Technology International Conference (CSTIC). -2017. -P. 1-3.Google Scholar
  35. 92.
    Liu J., Salmela O., Sarkka J., Morris J.E., Tegehall P., Andersson C. Reliability of Microtechnology: Interconnects, Devices and Systems. -Springer, 2011. -204p.Google Scholar
  36. 93.
    Kashyap C., Krauter B. A realizable driving point model for on-chip interconnect with inductance // ACM/IEEE 37th Design Automation Conference. -Los Angeles, 2000. -P. 190-195.Google Scholar
  37. 94.
    Kleveland Qi X., Yu B.Z. On-chip inductance modeling of VLSI interconnects // International Solid State Circuits Conference (ISSCC). -San Francisco, 2000. -P.172-173.Google Scholar
  38. 95.
    Massoud Y., Majors S., Bustami T., White J. Layout techniques for minimizing on-chip interconnect self-inductance // ACM/IEEE 35th Design Automation Conference. -San Francisco, 1998. -P. 566-571.Google Scholar
  39. 96.
    Wu B. High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging // IEEE Semiconductor Technology International Conference (CSTIC). -2017. -P. 1-3.Google Scholar
  40. 97.
    Dengi E.A., Rohrer R.A. Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling // ACM/IEEE 34th Design Automation Conference. -Anaheim, California, 1997. -P. 127-132.Google Scholar
  41. 98.
    Delorme N., Belliville M., Chilo J. Inductance and capacitance analytic formulas for VLSI interconnects // Electronics letters. -1996. -Vol.32, No. 11. -P. 996-997.CrossRefGoogle Scholar
  42. 99.
    Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of TTL circuits // SUAB, Vol. 1, Computer Engineering, Moscow, 1997. -P. 189-198. (in Russian)Google Scholar
  43. 100.
    Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of ECL circuits // SUAB, Vol. 2, Computer Engineering, Moscow, 1997.-P. 187-194. (in Russian)Google Scholar
  44. 101.
    Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of I2L circuits // SUAB, Vol. 3, Computer Engineering, Moscow, 1997. -P. 163-166. (in Russian)Google Scholar
  45. 102.
    Melikyan V. Sh., Vatyan A.O., Simonyan A. Sh. Delay models of digital VLSI Interconnects // RAs National Academy of Science and SEUA. Vol. 3, N 3, Yerevan, 1997. -P. 201-205. (in Armenian)Google Scholar
  46. 103.
    Melikyan V. Sh., Sargsyan S.M., Petrosyan D.A. Calculation model of parasitic inductances of inner interconnects of VLSI // Simulation, optimization, control, SEUA, Yerevan, Vol. 1, No. 7, 2004. -P. 59-68. (in Russian)Google Scholar
  47. 104.
    Melikyan V., Sargsyan S., Petrosyan D. A macromodel of internal interconnects of ICs // RAs National Academy of Science and SEUA. Vol. 57, No. 3, Yerevan, 2004. -P. 506-516. (in Armenian)Google Scholar
  48. 105.
    Davis J.A., De V.K., Meindl J.D. A stochastic wire-length distribution for gigascale integration (GSI). – Part I: Derivation and validation // IEEE Transactions on Electron Devices. -1998. -Vol. 45. -P. 580-589.Google Scholar
  49. 106.
    Wei H., Wang Z. A weighted average formula for efficient inductance and resistance extraction // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 996-999.Google Scholar
  50. 107.
    Ismail Y.I., Friedman E.G. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. -2000. -Vol. 8. -P. 195-206.CrossRefGoogle Scholar
  51. 108.
    Rao V.B. Delays analysis of the distributed RC line // ACM/IEEE 32nd Design Automation Conference. -San Francisco, 1995. -Vol. 12, No. 5. -P. 370-375.Google Scholar
  52. 109.
    Shepard K.L., Narayanan V., Elmendorf P.C., Cheng G. Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -San Jose, 1997. -P. 139-141.Google Scholar
  53. 110.
    Zhang L., Jing T., Hong X., Xu J., Xiong J., He L. Performance Optimization Global Routing with RLC Crosstalk Constraints // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 191-194.Google Scholar
  54. 111.
    Chen W.Y., Gupta S.K., Breuer M.A. Test Generation for Crosstalk-Induced Delay in Integrated Circuits // IEEE International Test Conference (ITC). -Washington, 1999. -P. 191-200.Google Scholar
  55. 112.
    Gupta A. Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology // IEEE Computing, Communication & Automation (ICCCA). -2015. -P. 1215-1219.Google Scholar
  56. 113.
    Caddemi A., Cardillo E.. A study on dynamic threshold for the crosstalk reduction in frequency-modulated radars // IEEE Computing and Electromagnetics International Workshop (CEM). -2017. -P. 29-30.Google Scholar
  57. 114.
    Khatri S.P., Brayton R.K., Sangiovanni-Vincentelli A.L. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. -Kluwer Academic Publishers, 2001. -144p.Google Scholar
  58. 115.
    Xu J., Hong X., Jing T., Cai Y., Gu J. A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design // IEEE Asia and South Pacific Design Automation Conference. -Kitakyushu, Japan, 2003. -Vol. E86-A, No. 12. -P. 847-850.Google Scholar
  59. 116.
    Servel G., Huret F., Paleczny E. Inductance Effect in Interconnect Coupling Noise // IEEE 5th Workshop on signal propagation on Interconnects. -Venice, 2001. -P. 74-81.Google Scholar
  60. 117.
    Archambeault B. PCB Design for Real-World Emi Control. -Kluwer Academic Publishers, 2002. -244p.Google Scholar
  61. 136.
    Melikyan V.Sh., Hovasapyan N.O., Manukyan G.G. Definition of noise immunity of digital VLSI//Interuniversity proceedings of YPI “Technical means and mathematical provision of computing systems”, Yerevan, 1988. -P. 60-62. (in Russian)Google Scholar
  62. 137.
    Fu J., Hong X., Cai Y., Luo Z. Decoupling Capacitor Allocation for Power Delivery Network Noise Reduction Based on Standard Cell Layouts // IEEE International conference on ASIC(ASICON). -Beijing, China, 2003. -Vol. 1. -P. 101-104.Google Scholar
  63. 138.
    Liou J.J., Krstic A., Jiang Y.M., Cheng K.T. Modeling, Testing and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. -2003. -Vol. 22, No. 6. -P. 756-769.Google Scholar
  64. 139.
    Melikyan V., Sargsyan S. A simulation method of considering parasitic effects of supply buses of ICs // Information Technologies and Management. Vol. 1, Yerevan, 2004. -P. 34-48. (in Armenian)Google Scholar
  65. 140.
    Sotiriadis P., Chandrakasan A. Reducing bus delay in sub-micron technology using coding // IEEE Asia and South Pacific Design Automation Conference. -Japan, Yokohama, 2001. -P. 109-114.Google Scholar
  66. 141.
    Kleveland B., Qi X., Madden L. Line inductance extraction and modeling in real chip with power grid // International Electron Devices Meeting. -1999. -P. 901-904.Google Scholar
  67. 142.
    Saleh R., Hussain Z., Rochel S., Overhauser D. Clock Verification in the Presence of IR-drop in the Power Distribution Network // IEEE Transaction on CAD of IC and Systems. -2000. -Vol. 19, No. 6. -P. 635-644.Google Scholar
  68. 143.
    Aragones X., Gonzales J., Rubio A. Analysis and Solutions for switching Noise Coupling in Mixed-Signal ICs. -Kluwer Academic Publishers, 1999. -236p.Google Scholar
  69. 144.
    Charbon E., Gharpurey R., Miliozzi P., Meyer R.G., Sangiovanni-Vincentelli A.L. Substrate Noise Analysis and Optimization for IC Design. -Kluwer Academic Publishers, 2001. -200p.Google Scholar
  70. 145.
    Van Heijningen M., Compiet J., Wambacq P., Donnay S., Engels M., Bolsens L. Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates // IEEE Journal Solid-State Circuits. -2000. -Vol. 35. -P. 1002-1008.Google Scholar
  71. 146.
    Panda R., Blaauw D., Chaudry R., Zolotov V., Young B., Ramaraju R. Model and Analysis for Combined Package and On-Chip Power Grid Simulation // International Symposium on Low Power Electronics and Design (ISLPED). -Huntington Beach, California, 2000. -P. 179-184.Google Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Vazgen Melikyan
    • 1
  1. 1.Director of Educational DepartmentSynopsys Armenia CJSCYerevanArmenia

Personalised recommendations