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Extracting of High-Level Structural Representation from VLSI Circuit Description Using Tangled Logic Structures

  • Andrey Trukhachev
  • Natalia Ivanova
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 636)

Abstract

This paper proposes a method of automatic VLSI circuit analysis. We propose pattern-free, technology independent method for extracting of functional blocks with irregular structure. On the first step, transistors are grouped by their structure. Groups with irregular structure are highly interconnected to each other. Detecting Tangled Logic Structures (TLS) with a GTL-depended linear ordering and genetic algorithm divides the circuit due to its functional structure and forms the gate-level VLSI circuit. High-level functional blocks in circuit description consist of gate-level cells groups, which are also highly interconnected. After TLS-blocks extracting, it is possible to describe their function. TLS-blocks are smaller, represent a cell of high-level circuit, and are thus more suitable for further functional circuit analysis than a gate-level VLSI circuit.

The experimental data obtained as a result of the principle electrical circuits of different degree of connectivity analysis confirmed the effectiveness of the proposed method.

Keywords

VLSI Genetic algorithm Tangled logic Functional circuit analysis 

Notes

Acknowledgment

This work was supported by the MEPhI Academic Excellence Project (agreement with the Ministry of Education and Science of the Russian Federation of August 27, 2013, project no. 02.a03.21.0005).

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Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  1. 1.National Research Nuclear University MEPhI (Moscow Engineering Physics Institute)MoscowRussia
  2. 2.Bauman Moscow State UniversityMoscowRussia

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