TCAD Simulation of Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors
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Indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are simulated using TCAD software. Nonlinearities observed in fabricated devices are obtained through simulation and corresponding physical characteristics are further investigated. For small channel length (below 1 µm) TFTs’ simulations show short channel effects, namely drain-induced barrier lowering (DIBL), and effectively source-channel barrier is shown to decrease with drain bias. Simulations with increasing shallow donor-like states result in transfer characteristics presenting hump-like behavior as typically observed after gate bias stress. Additionally, dual-gate architecture is simulated, exhibiting threshold voltage modulation by the second gate biasing.
KeywordsIGZO TCAD simulation DOS TFT CPS
Oxide TFTs are nowadays starting to play an important role in display industry, with leading companies as LG using them in the backplane of recent products, such as curved organic light emitting device (OLED) TV sets. Still, significant advances in the current state-of-the-art of oxide TFT technology are required before high performance fully transparent, flexible, low-cost and low-power dissipation electronics reach the maturity level required for commercialization. The implementation of Technology Computer-Aided Design (TCAD) [1, 2] tools for simulation of devices at a physical level can lead to understanding on how to further improve fabrication processes, material properties and device architectures. The ultimate goal is to enhance the performance of amorphous oxide TFTs, mimicking the routes followed for single-crystalline CMOS, a-Si and poly-Si technologies. Embedding physically-extracted parameters from the fabricated devices into the models for simulation, accurate models can be built and prediction on how changes in materials and processes affect physical response of the oxide TFTs can be achieved. This can allow viable process and device development and, simultaneously, understanding, the otherwise difficult or even impossible to extract physical characteristics behind device operation. Some specific goals to be addressed are referred next.
As performance of amorphous oxide semiconductors (AOS) is controlled by the density of states (DOS) in a given material, and TCAD simulation is based in the DOS , it can provide understanding of the specific nature of states causing performance differences among different AOS. This can be used for instance to achieve a suitable and sustainable indium-free replacement for IGZO. Modeled IGZO TFTs based on DOS extracted from different techniques have shown to agree very well with measured characteristics, without employing any fitting parameter [4, 5]. Instabilities in oxide TFTs can be further investigated with TCAD, by implementing charge-trapping and defect creation in the simulations, allowing to understand the specific physical causes of degradation in TFTs, typically associated with Gate/Drain Bias Stress, illumination and temperature. Correlations between the defect-creation and the device performance degradation have been reported , with localization of defect creation being also investigated by means of simulations . Some effects that limit device performance are related to device architecture, as parasitic capacitances that limit the maximum operation frequency, and short channel effects (SCE), which limit the scalability of the technology. As architectures can be arbitrarily defined in TCAD simulation optimization and understanding of physical phenomena in different geometries appears as a great advantage. Moreover, as recently more and more TFT architectures are proposed (e.g. dual-gate, floating-capping-metal, bulk-accumulation  and dual-active layer TFTs), TCAD can accelerate the optimization of those configurations, reducing fabrication runs and elucidating the physics behind the electrical behavior of each architecture .
In this work the short channel effect Drain Induced Barrier Lowering (DIBL) is shown with TCAD simulation in μm-scale IGZO TFTs. To the best of the authors’ knowledge it’s the first time that the barrier level for different drain bias is displayed for μm-scale oxide TFTs.
2 Integration in Cyber Physical Systems
Amorphous oxide electronics allow for production in a wide range of substrates, notably, inexpensive flexible and/or transparent substrates, as they can be processed at low temperatures (while still maintaining good performance) and have large area uniformity due to their amorphous nature. This way, they can be integrated into a wider range of systems, rather than their silicon technology counterparts. This technology thus shows to have great applicability in Cyber Physical Systems (CPS). In the CPS 5Cs architecture, amorphous oxides can be integrated in the Connection and the Conversion layers. In the Connection level they present the already discussed advantages of being applicable in wide range of substrates, as flexible and transparent ones. Several applications have already been reported as gas sensors , touch-panels  and even biological sensors . Integrated with the connection level, the technology can also be in the conversion level as they have performance that allow for the processing of the information received at the Connection level. In fact, one of the current trends of oxide TFT technology is precisely focused on full integration and in increasingly more complex circuits, including signal processing, amplification and, ultimately, analog-to-digital conversion .
3 TCAD Simulation
For simulation purposes the TCAD Silvaco’s 2D ATLASTM was used. A similar configuration than that of fabricated devices was employed. An electron mobility of 16 cm2 (V s)−1 and electron concentration of 1016 cm−3 in the a-IGZO was assumed. Both fabricated and simulated TFTs have a channel length of 20 μm unless otherwise is specified. Channel width of the characterized TFTs is 20 μm and for simulated devices the obtained drain current in 2D simulation is factored in order to correspond to a 20 μm width channel TFT.
3.1 Short Channel Effects
By extracting the conduction band energy level across the channel the decreasing of the barrier between source and semiconductor with increasing drain bias is clear, as shown in Fig. 3.
3.2 Hump in Transfer Characteristics
3.3 Dual-Gate TFT
4 Conclusions and Future Work
TCAD simulations have demonstrated to be a powerful tool to improve understanding on amorphous oxide TFTs and reduce fabricated batches and costs. Short channel effects have been shown in simulations of IGZO TFTs, and these are in agreement to what was verified in fabricated devices by sputtering. Transfer characteristics shifted with drain bias, explained as DIBL, and the barrier has been effectively seen to reduce with drain bias observing the simulated conduction band energy in the IGZO. Further investigation on the SCEs, such as understanding the role of the Schottky barrier, might elucidate on how to suppress these effects. As for the hump behavior, simulation showed that it may be somehow related to shallow donor-like state creation. Further investigation on how specific DOS affect the device characteristics will lead to understanding the mechanisms of degradation in the oxide TFTs. Finally, simulation of a double-gate TFT was employed, and the Von modulation by the second gate bias was observed. This modulation can be used to achieve enhancement mode TFTs as preferred for application in circuit.
This work is funded by FEDER funds through the COMPETE 2020 Programme and National Funds through FCT - Portuguese Foundation for Science and Technology under the Project Nos. UID/CTM/50025/2013 and EXCL/CTM-NAN/0201/2012. The work has also received funding from the European Communities 7th Framework Programme under grant agreement ICT-2013-10-611070 (i-FLEXIS project) and from H2020 program under ICT-03-2014-644631 (ROLL-OUT project).
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