Computation of Cores in Big Datasets: An FPGA Approach
In this paper we propose the FPGA and softcore CPU supported device for performing core calculation for large datasets using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solution inside FPGA. Sizes of the datasets were in range 1 000 to 10 000 000 objects. Results show the big acceleration in terms of the computation time using hardware supporting core generation unit.
KeywordsRough sets FPGA Hardware Core
The research is supported by the Polish National Science Centre under the grant 2012/07/B/ST6/01504 (Jaroslaw Stepaniuk, Maciej Kopczynski) and by the scientific grant S/WI/3/2013 (Tomasz Grzes).
- 3.Kanasugi, A., Yokoyama, A.: A basic design for rough set processor. In: The 15th Annual Conference of Japanese Society for Artificial Intelligence (2001)Google Scholar
- 5.Kopczyński, M., Grześ, T., Stepaniuk, J.: FPGA in rough-granular computing : reduct generation. In: WI 2014 : The 2014 IEEE/WCI/ACM International Joint Conferences on Web Intelligence, vol. 2, pp. 364–370. IEEE Computer Society, Warsaw (2014)Google Scholar
- 6.Kopczynski, M., Grzes, T., Stepaniuk, J.: Generating core in rough set theory: design and implementation on FPGA. In: Kryszkiewicz, M., Cornelis, C., Ciucci, D., Medina-Moreno, J., Motoda, H., Raś, Z.W. (eds.) RSEISP 2014. LNCS, vol. 8537, pp. 209–216. Springer, Heidelberg (2014) Google Scholar
- 7.Lewis, T., Perkowski, M., Jozwiak, L.: Learning in hardware: architecture and implementation of an FPGA-based rough set machine. In: 25th Euromicro Conference (EUROMICRO 1999), vol. 1, p. 1326 (1999)Google Scholar
- 8.Lichman, M.: UCI Machine Learning Repository, Irvine, CA: University of California, School of Information and Computer Science (2013). http://archive.ics.uci.edu/ml
- 15.Stepaniuk, J., Kopczyński, M., Grześ, T.: The first step toward processor for rough set methods. Fundamenta Informaticae 127, 429–443 (2013)Google Scholar
- 16.Tiwari, K.S., Kothari, A.G.: Design and implementation of rough set algorithms on FPGA: a survey. (IJARAI) Int. J. Adv. Res. Artif. Intell. 3(9), 14–23 (2014)Google Scholar
Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 2.5 International License (http://creativecommons.org/licenses/by-nc/2.5/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.
The images or other third party material in this chapter are included in the chapter's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the chapter's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder.