Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models

SRAMs are widely used in many applications as caches etc. due to their fast access speed but also contribute significantly to area cost and power consumption. Particularly in system-on-chip design, dedicated SRAMs with optimized architecture and circuits are often applied for achieving low-power. The optimization of those dedicated SRAMs for lowest possible power at a given performance is a quite challenging task because of the complexity of the design space. An attractive approach is to perform a quantitative optimization based on cost models. Such cost models not only support the optimization process but also allow for early cost estimation in the system conception phase. The focus of the study is laid on the power cost considering the increasingly significant role of power consumption of SRAMs.

From the low-power perspective, SRAMs with hierarchical architecture, as described e.g. in [1, 2, 3, 4], are very attractive choices. A quantitative optimization approach for the hierarchical-architecture SRAMs deserves further research.

Figure 1 provides a block diagram of such a hierarchical-architecture SRAM of 2 K words with a 45 bit-wordlength. Apart from the timing control circuits, the memory matrix and the address decoders dominate the total power consumption. These two components exhibit a large design space regarding the underlying architecture and circuits. In the hierarchical architecture the memory matrix is typically organized in 2 ^m (m = 3) columns. Each column includes a local timing generator, a bit cell column and a local wordline decoder. A bit-cell column consists of 2 ⁿ (n = 4) local blocks and a local block is sub-divided into 2 ^u (u = 4) words vertically. Thereby, the long bitlines and wordlines are both divided into global and local lines for reducing the switched capacitances. Moreover, the use of local sense amplifiers further reduces the power consumption by decreasing the signal swing on the long interconnects. Furthermore, the bit cell column could consist of various efficient circuits, such as assist circuits [1], stable bit cell and bit-interleaved technique [2] and pre-charge schemes [3, 5]. Apparently a large design space exists for selecting hardware-efficient architectures and the underlying circuits. Especially for SRAMs with different capacities and features, the time to market constraints make design space difficult to be explored. Therefore, there is a strong demand to come up with a cost model, by which architecture parameters, local circuits and power reduction techniques are characterized and quantitatively analyzed.

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A predictive and mature design flow for on-chip SRAMs must simultaneously consider energy (E), area (A) and speed (T) properties. For this reason a cost estimation environment is under elaboration serving as an efficient design aid and a quantitative optimization tool. Figure 2 sketches the overall flowchart of this environment. The SRAM specifications are given by the capacity in number of words and wordlength. The first task is to determine the optimal architecture and most effective circuit techniques. A hierarchical architecture is taken as the subject to be analyzed and optimized. The architectures are specified by the partitioning parameters (m, n, u). Here, parameter m is the column address decoder width, which denotes the number of columns (M = 2 ^m ) and n is the row address decoder width, which denotes the number of rows (N = 2 ⁿ ) in a memory matrix. Parameter u is the unit address decoder width, which denotes the number of cells (U = 2 ^u ) in a column unit. On the whole, the three parameters define the partitioning and organization of a hierarchical-architecture SRAM with a total capacity of M*N*U words being equal to 2 ^a address bits with wordlength (w). The decomposition and combination possibilities of the three parameters are explored for selecting the optimal architecture partitioning.

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Besides the choices related to partitioning regarding the design space, there exists a wide choice of various energy-efficient circuit techniques. These circuit techniques, such as the ones related to the bit cells, assist circuits and local sense amplifiers (LSA) cause additional overhead and complexity to the overall design. The consumed energy is difficult to evaluate and estimate since it depends on the context in which these circuits are used. Their non-standard features cannot longer be characterized using the available models which only include standard features. Hence there must be a quantitative benchmarking tool to assess these circuits and techniques. Accordingly, their respective power consumption should be estimated and compared while using different configurations so that the optimal one can be selected. A pre-characterization methodology is employed for capturing their distinct features and quantifying the analysis. With these 2 sets of inputs, partitioning parameters and specific circuit techniques, a design-space exploration is carried out, while building a cost (A, T, E) model for on-chip SRAMs. This way a Pareto-optimization is carried out by trading off the three costs (A, T, E). Finally the design decisions regarding architecture and circuits are made.

The idea of a cost-model based pre-characterization of elementary components (i.e. logic gates and bit cells) is further explained in Fig. 3. Given specification parameters (a, w), all the possibilities of the partitioning parameter (m, n, u) are generated and then these possibilities are evaluated by the presented cost model. An ATE cost database is built by proper circuit simulation of extracted component netlists, which depends on the use case (e.g. V _dd , V _bias ), technology corners, temperature, frequency and gate sizes.

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• The area can be estimated by a parameterized floor plan estimation and an accumulation of elementary widths and height values (e.g. W _components , H _components ).

• In the energy model, the elementary energy values of basic circuits (e.g. E _gate ) are accumulated with the partitioning parameters and switching activity probabilities. The interconnect energy is estimated from the wire length and the energy per unit length (E _{wire_unit} ). Finally the total energy consumption is derived by an accumulation of elementary energy (e.g. E _bl ) from all used circuit components.

• The speed can also be derived by using the cost data base (e.g. t _slope , W _wire , C _load, C _input ) and a elementary delay accumulation along the critical path involving long resistance-capacitance interconnects.

In this contribution, we focus on the energy cost model and the relevant optimization approach. In the proposed model, only a few necessary basic circuit components (i.e. basic bit cells) need to be characterized. These circuit components could be verified by a number of Monte-Carlo simulations for ensuring robustness. Moreover, the pre-characterization including simulation time and model building only requires couple of hours and afterwards the estimation results can be acquired in a few minutes. Therefore, the total effort of the cost model is much less compared to a complete reference design.

A conventional hierarchical low-power SRAM organization including address decoders and memory matrices is illustrated in Fig. 4. It is partitioned into 2 ^(m+n) blocks which are organized as an array of M = 2 ^m block columns and N = 2 ⁿ block rows, while m and n are dependent on the decompositions of column and row address decoders. The outputs of these two pre-decoders, 2 ^m column select (CS) and 2 ⁿ row select (RS) signals, are further decoded by NOR or NAND gates for generating the 2 ^(m+n) Blockact signals for selecting a specific block. Each block is composed of U = 2 ^u words placed vertically and it includes w column units. The column unit is considered as a basic unit for the memory matrix, which includes 2 ^u cells per column unit and one LSA. A unit decoder and the row decoder generate 2 ^(u+n) global wordlines (GWL) at the output to access the selected row in the block. Afterwards, the GWLs and Blockact signals are further decoded to 2 ^(m+n+u) local wordlines (LWL) to access the selected word. In this way, bitline and wordline capacitances are reduced for meeting the low-power requirement. Also, the introduction of LSA reduces the voltage swing on global bitlines.

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As discussed before, the memory matrix is organized into M = 2 ^m block columns. In these block columns various complex but efficient circuits are utilized. In Fig. 5, a block column is shown for exemplifying these specific circuits. It is composed of a local timing-control signal generator, a LWL decoder and a bit cell column. In the local timing-control signal generator, the global timing pulse signals are combined with the Blockact signals to generate local timing pulse signals for the N = 2 ⁿ blocks. Similarly in the LWL decoder, the GWL signals running through the whole memory matrix are combined with the Blockact signals to generate LWL signals for each word in the bit cell column. The bit cell column is instantiated by high-threshold voltage bit cells with reverse back-biasing long channels, equalizer pre-charge scheme, read/write assist circuits and a wide local sense amplifier [5]. A block in a bit cell column is composed of w column units. Each column unit includes U = 2 ^u 6T cells, assist circuits and a LSA.

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The choice of m and w defines the parasitic wordline capacitances and the wordline structure. Either a non-divided wordline (non-DWL) or a DWL structure can be selected according to the capacity and wordlength. The parameter n defines the bitline hierarchy and therewith affects the global and local bitline capacitances. Especially, charging and discharging the bitlines contributes significantly to the overall power consumption. The number of cells u in one column unit determines to a large extent the minimum energy consumption for one operation. The n and u must be carefully selected for trading the least frequent use of LSAs and the minimum switching capacitances.

SRAMs typically include two major contributors to power consumption: the address decoders and the memory matrices. In the hierarchical architecture (Fig. 4), the way of dividing and combining the address decoders determines how the memory matrix is partitioned into sub-blocks. A probabilistic estimation approach is employed for estimating the switching activity and power consumption of the address decoder especially regarding whether or not a distributed wordline structure is used. The memory matrices including complex assist and periphery circuits, which consume a large portion of power, were also modeled and characterized. Four basic circuit templates and a power estimation method are proposed to extract and describe the architecture and circuit characteristics for the hierarchical architecture. The specific circuits used within the four circuit templates can be altered without changing the estimation approach itself. Various power reduction techniques, e.g. precharge schemes in [3, 5], circuit techniques in [1, 2, 5], can be pre-characterized and benchmarked in the same configurations, which makes this model very appropriate for customized SRAM designs.

For an SRAM with a address bits comprising a capacity of 2 ^a words with a wordlength w, a flow chart of the power estimation model is shown in Fig. 6. The two portions constituting the power model are the address decoder and the memory matrix. For the address decoder, a address bits are divided into three sections (m, n, u), which are decoded by the three pre-decoders including column, row and unit decoder. In the 2nd stage, a block decoder combines RS and CS signals to generate the Blockact signals. A word-row decoder uses RS and US signals for generating the GWL signals. In the 3rd step, a word decoder uses both Blockact and GWL signals to produce the LWL signals. The three decoders are all composed of NAND or NOR gates and are arranged in a matrix-like select circuit. The sum of the power consumed by the pre-decoders and the matrix-like select circuits provides an estimate of the total power estimation of the whole address decoder. For the memory matrix, the parameters (m, n, u) are used for quantifying and analyzing the bitline and wordline structure. Since the parameters represent the number of the sub-modules and determine the final SRAM architecture, their respective impact is analyzed and attributed to the components of the memory matrix. The parameter m determines the capacitances of the horizontal global wordlines (HGBL) and the amount of pass transistors used as column selectors. The number of the Blockact and GWL signals affects the capacitances of vertical global bitlines (VGBL) and GWLs respectively. Finally, the choice of u has an impact on the power consumption from LBLs of accessed cells, assist circuits, and LSAs. Therefore, a quantitative analysis about the dependency relations is made between the combinations of (m, n, u) and all the power contributors. Given the specifications a and w, all the possible partitioning parameters (m, n, u) are evaluated by estimating the respective power consumption. Finally, the optimal parameter selection is saved for fulfilling different ATE design requirements, such as minimum power consumption.

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The contribution of the memory matrix to the total memory access energy is dominated by the cycle-based pre-charge and discharge of long bitlines. For low-power memory matrix designs, assist circuits, bit cells and pre-charge schemes span a large design space complicating the power modeling. Their complex features bring significant influences on the layout placement location and the switching capacitances. Accordingly, the total energy cannot be computed by directivity accumulating their respective individual energies. Additionally, the use of LSAs in [1] brings low-voltage swing at global bitlines and high-voltage swing at local bitlines. The complexity with multiple VDD plays at larger scale which makes it more difficult to estimate the power consumption. As before, the variable partitioning parameters (m, n, u and w) result in different access gates and parasitic capacitances due to different wire lengths. Another challenge is that read, write and standby operations must be considered separately, including a hierarchical bitline structure and the memory cell toggling state. In order to solve these issues, four circuit templates are proposed to act as a black box for pre-characterization. In this way a database depending on the use case (V_DDH and V_DDL), technology corners, temperature and the characteristics of gates (width) and wires is generated. Finally, the elementary energies from assist circuits, bit cells and vertical global bitlines are separated by our estimation approach. Combined with the partitioning parameters the power consumed by the overall memory matrix is estimated accurately. Leakage power is estimated in a similar way.

5.1 Four Circuit Templates

Four circuit templates based on the circuits given in [5] are presented as basic circuit elements for characterizing the complex assist circuits and specific bit cells. As shown in Fig. 11, a single cell circuit template is presented first to separate the elementary energy from multi cell circuits. Its dynamic energy consists of contributions from the local bitline of each cell (E _lbl ), the local wordline (E _lwl ) and the periphery circuits including precharge circuits (E _pre ), read/write assist transistors (E _ren /E _wen ) and LSA (E _lsa ). For pre-characterization the customized design a layout for the single cell circuit template is drawn. This way the dynamic energy (E ₁ ) and static power (P _static1 ) are obtained by extracted-netlist simulation

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$$ E_{1} = E_{pre} + E_{ren} + E_{lwl} + E_{lsa} + E_{lbl} . $$

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For separating the elementary energy from the local bitline of each cell (E _lbl ), a column unit circuit template is drawn in Fig. 12. Its dynamic energy (E ₂ ) and static power (P _static2 ) are also obtained from extracted-netlist simulation. In the same way its total energy (E ₂ ) is decomposed to several elementary energies. By taking the LSA and periphery circuits apart, the energy from the 1–8 cells are linearly interpolated. Thereby, the energy consumed by local bitline of each cell (E _lbl ) is derived

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$$ E_{2} = E_{pre} + E_{ren} + E_{lwl} + E_{lsa} + 8 \cdot E_{lbl} $$

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$$ E_{lbl} = {{\left( {E_{2} - E_{1} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{2} - E_{1} } \right)} 7}} \right. \kern-0pt} 7} $$

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For further separating the elementary energy from the periphery circuits, a row unit circuit template is designed as shown in Fig. 13. In the same manner this fraction is separated by calculating E ₃ and E ₂ .

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$$ E_{3} = 8 \cdot \left( {E_{pre} + E_{ren} + E_{lbl} } \right) + E_{lwl} + E_{lsa} $$

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$$ E_{pre} + E_{ren} + E_{lwl} + E_{lsa} = {{\left( {E_{3} - E_{2} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{3} - E_{2} } \right)} 7}} \right. \kern-0pt} 7} . $$

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Similarly, a column circuit template is created in Fig. 14, by which the elementary energy consumed by vertical global bitlines (E _vgbl ) is separated.

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$$ E_{4} = E_{pre} + E_{ren} + E_{lwl} + E_{lsa} + 8 \cdot E_{lbl} + 7 \cdot E_{vgbl} $$

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$$ E_{vgbl} = {{\left( {E_{4} - E_{2} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{4} - E_{2} } \right)} 7}} \right. \kern-0pt} 7} . $$

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Since E ₁ …E ₄ and P _static1 …P _static4 are pre-characterized by simulating the extracted-netlists of the four circuit templates, the elementary energy values E _lbl , E _{pre+ren+lwl+lsa} , E _vgbl can be derived. This way the dynamic energy for read/write operations and static power of the four circuit templates are obtained. It is assumed that a toggle condition occurs for each write operation. As before, the simulation configuration is TT corner, 25°C, 400 MHz and 0.9 V supply voltage in 40 nm CMOS technology. The voltage swing of vgbl pair was chosen to 300 mV to guarantee robust operations. The estimation approach is the same for other technology corners but the pre-characterization must be modified based on a Monte-Carlo simulation.

Read Operation. As mentioned before, read and write operations are studied separately due to their different characteristics. For a read operation of a hierarchical SRAM with the use of LSAs, the bitline/wordline capacitance, the LSA along with read/write assist and precharge circuit are the main energy consuming components. The dynamic energies E _lbl and E _lwl are the sum of the energies due to the wiring capacitance itself and the capacitances attached to the memory cells. In addition, the energy consumed by the static components of the unselected memory matrices is attributed to the dynamic energy, comprising a significant portion. The static power (P _static1 …P _static4 ) of the four circuit templates can be acquired using the same approach as before by separating the dynamic energy of each component. Particularly the pass transistors acting as column selectors are also included in the model. The static power of the global sense amplifiers (GSA) and the pass transistors are obtained by multiplying their count with the static power of two simple circuits: a GSA circuit and a pass transistor circuit. As a consequence, according to the parameters of memory matrix defined above for a hierarchical architecture, standby power of a column block can be estimated as

$$ \begin{aligned} P_{static\_col} &= w \cdot \left( {U \cdot N \cdot P_{lbl\_staic} + \mathop P\nolimits_{gsa\_pass\_static} } \right) + w \cdot \left( {P_{{pre\_{\text{static}}}} + P_{ren\_static} + P_{lwl\_static} + P_{lsa\_static} } \right) \hfill \\ & = w \cdot \left( {U \cdot N \cdot {{\left( {P_{static2} - P_{static1} } \right)} \mathord{\left/ {\vphantom {{\left( {P_{static2} - P_{static1} } \right)} 7}} \right. \kern-0pt} 7} + P_{gsa\_pass\_static} )} \right) + w \cdot \left( {{{\left( {P_{static3} - P_{static2} } \right)} \mathord{\left/ {\vphantom {{\left( {P_{static3} - P_{static2} } \right)} 7}} \right. \kern-0pt} 7}} \right)\end{aligned} $$

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Finally, the overall dynamic energy of reading a bit from the memory matrix is estimated. The partitioning parameters (m, n, u) are converted to the number (M = 2 ^m , N = 2 ⁿ , U = 2 ^u ) of partitioned components in memory matrix. The total energy is calculated by parameterized accumulating the elementary energies (E _lbl , E _{pre+ren+lwl+lsa} , E _vgbl , E _gsa , E _pass ). Particularly, the energy from the unselected parts in the memory matrices is calculated independently and then added to the total dynamic energy.

$$ \begin{aligned} E_{read\_bit} =& w \cdot U \cdot E_{lbl} + E_{vgbl} \cdot \left( {N - 1} \right) + E_{gsa} + M \cdot w \cdot E_{pass} \hfill \\ & + \left( {E_{pre} + E_{ren} + E_{lwl} + E_{lsa} } \right) + (M - 1) \cdot P_{static\_col} /f \hfill \\ =& w \cdot U \cdot {{\left( {E_{2} - E_{1} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{2} - E_{1} } \right)} 7}} \right. \kern-0pt} 7} + \left( {N - 1} \right) \cdot {{\left( {E_{4} - E_{2} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{4} - E_{2} } \right)} 7}} \right. \kern-0pt} 7} + E_{gsa} + M \cdot w \cdot E_{pass} \hfill \\& + {{\left( {E_{3} - E_{2} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{3} - E_{2} } \right)} 7}} \right. \kern-0pt} 7} + (M - 1)P_{static\_col} /f .\end{aligned} $$

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Write Operation. For the write operation, the method to separate the dynamic write energy of each component is similar but using the pre-characterized write energies in Table 4. Particularly, the toggle state is not considered here because the energy of the write operation is obtained assuming a toggle event for each write. A toggle state does not occur all the time and its corresponding energy can be estimated using a similar approach as in [2] using a toggling probability. As a result, the write cycle energy can be calculated as follows.

Table 4.

Energy of four circuit templates (TT, 25°, 400 MHz, V_DDH = 0.9 V, V_DDL = 0.3 V)

Circuit Templates		Cell	Column unit	Row unit	Column
Dynamic energy (pJ)	Write	4.26	5.25	25.75	12.58
	Read	2.91	3.71	22.47	5.88
Static power (nW)		3.23	24.37	25.88	195.74

$$ \begin{aligned} E_{write\_bit} =& w \cdot U \cdot E_{lbl}^{'} + \left( {E_{{pr{\text{e}}}}^{ '} } \right. + E_{wen}^{'} + \left. {E_{lwl}^{'} + E_{lsa}^{'} } \right) \hfill \\ & + \left( {N - 1} \right) \cdot E_{vgbl}^{'} + (M - 1)P_{standby\_col} /f \hfill \\= &w \cdot U \cdot {{\left( {E_{2}^{'} - E_{1}^{'} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{2}^{'} - E_{1}^{'} } \right)} 7}} \right. \kern-0pt} 7} + {{\left( {E_{3}^{'} - E_{2}^{'} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{3}^{'} - E_{2}^{'} } \right)} 7}} \right. \kern-0pt} 7} \hfill \\ & + \left( {N - 1} \right) \cdot {{\left( {E_{4}^{'} - E_{2}^{'} } \right)} \mathord{\left/ {\vphantom {{\left( {E_{4}^{'} - E_{2}^{'} } \right)} 7}} \right. \kern-0pt} 7} + (M - 1) \cdot P_{standby\_col} /f. \end{aligned} $$

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5.2 Verification of Memory Matrix Model

Several memory matrices have been simulated in 40-nm CMOS technology to validate the model equations above. In Fig. 15 the dynamic power break-down of a 64-KByte memory matrix is shown. It is observed that the energy of local bitlines dominates the power consumption in a memory matrix as compared to the other circuits.

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Figure 16 shows a comparison of simulation and estimation data for four memory matrices of different capacities (64, 128, 256, 1 K). Assuming a read access operation the four extracted-netlists were simulated using the same configuration. As shown in Table 5, the dynamic energies are compared to the estimated data and the differences are below 10 %. For the leakage power, the same comparisons are performed and the estimation errors are also below 10 %.

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Table 5.

Model Estimation Errors of the four capacities (TT, 25°, 400 MHz, V_DDH = 0.9 V, V_DDL = 0.3 V)

Capacity	64 × 8 bit	128 × 8 bit	256 × 8 bit	1024 × 8 bit
Dynamic energy	−5 %	−1 %	9 %	3 %
Static power	−4 %	−4 %	−5 %	2 %

To further demonstrate the accuracy, four memory matrices with a fixed number of 64 words and with word lengths 8, 16, 32, 64 are implemented. As shown in Fig. 17 the estimation data are comparable to extracted-netlist simulation data. Both for dynamic energy and leakage power the estimation error remains below 10 %, as listed in Table 6.

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Table 6.

Model Estimation Errors of the four word lengths (TT, 25°, 400 MHz, V_DDH = 0.9 V, V_DDL = 0.3 V)

Word lengths	64 × 8 bit	64 × 16 bit	64 × 32 bit	64 × 64 bit
Dynamic energy	−5 %	−5 %	−5 %	−7 %
Static power	−4 %	−4 %	−3 %	−6 %

The power model created in this work takes all the dominating power contributors of on-chip SRAMs into account, which include an address decoder, memory cells and assists circuits, local and global sense amplifiers, driver circuits and interconnect capacitance. Figure 18 shows the power model applied for estimating the power consumption of SRAMs for various capacities and wordlengths. Minimum read dynamic power data is given due to more frequent read operation in caches. The model is applicable for capacities ranging from 16 to 1 M words and four wordlengths (8, 16, 32, 64). The figure illustrates how DWL and hierarchical LSA architecture affect the read power of SRAMs as function of different capacities and wordlengths. Moreover it indicates the different power contributions from address decoder and memory matrix to the dynamic read power.

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In addition, the power model can be used for optimizing a specific SRAM by determining the optimal parameter combination. As discussed before, many possibilities exist for partitioning the memory matrix, the corresponding address decoder, given the three parameters partitioning parameters (m, n, u), and many options for circuit implementations. Depending on the optimization criteria parameter combinations are picked from all possible implementations options. Note that the impact of process variations on leakage power is included in the power model.

A Pareto-optimization is made by considering silicon area and read power of the different partitioning parameters. Figure 19 shows how to use this approach to optimize a 1 K Byte SRAM for achieving a power and area tradeoff. In the scatter plot, there are ten architectures presenting relatively good area and power, which are picked from all the generated architectures. Four Pareto-optimal implementations are marked, in which two architectures deliver low area and the other two deliver low read power. Depending on the user’s requirements a selection can be made, for instance the green point deliving a favorable area/power tradoff.

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Figure 20 shows a direct area/power break-down for the same ten possible architectures in Fig. 19. The contributions of the address decoder and memory matrix to the overall area and read power are shown and analyzed quantitatively. Between the worst case and best case solution a difference is observed for area and power up to 41 % and 62 % respectively.

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In this chapter, a new method for power optimization of on-chip SRAMs comprising a hierarchical architecture was described. The method is based on a power model including various energy-efficient circuits and techniques. The introduction of the probabilistic estimation approach and the use of circuit templates provide quantified switching activities and pre-characterized customized circuits separately. Simultaneously the hierarchical architecture regarding many partitioning choices is defined by the partitioning parameters. The power model is verified by a variety of extracted-netlist simulations and it consistently exhibits good accuracy.

As a quantitative parameter optimization tool, this approach allows a fast and accurate power estimation of SRAMs comprising various capacities and wordlengths. In a hierarchical-architecture SRAM, the impact of partitioning with circuit selections on power and area were evaluated. The optimal architecture and circuits can be identified very quickly and accurately which leads to a SRAM specification with an achievable and attractive power consumption and silicon area. Moreover, this approach allows an easy tradeoff between area and power for meeting different design requirements. Furthermore, the power model can also be employed as a customized benchmark for comparing various local circuits using the same architecture. Finally, this approach can easily be extended to other CMOS technologies due to its circuit templates and switching activity analysis.