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A Multiple Compatible Compression Scheme Based on Tri-state Signal

  • Tian ChenEmail author
  • Yongsheng Zuo
  • Xin An
  • Fuji Ren
Conference paper
  • 17 Downloads
Part of the Studies in Distributed Intelligence book series (SDI)

Abstract

A novel test data compression scheme based on the tri-state signal is proposed to solve the problem of increasing embedded chip test data in the development of Smart City. Firstly, partial inputs reduction is performed on the test set, and the don’t care bits proportion is improved by merging the test patterns with a high bit ratio so that the compatibility of each test pattern is improved. After using the inputs reduction technology, using the characteristics of the tri-state signal, the test set is divided into several sub-segments and uses the tri-state signal to compress the sub-segments with compatible coding, and the compression rate of the test set is improved by considering multiple compatible rules. The experimental results show that compared with the previous work results, the proposed scheme achieves a good compression ratio, the average test compression ratio can reach 82.15%. At the same time, the test power and area overhead are not significantly improved.

Keywords

Compression Automatic test equipment Circuit 

Notes

Acknowledgements

This work sponsored by: The Key Program of the National Natural Science Foundation of China (Grant No. 61432004); The National Natural Science Foundation of China (Grant No.61474035, No.61204046, No.61502140); NSFC-Shenzhen Joint Foundation (Key Project) (Grant No.U1613217).

References

  1. 1.
    S. Mirthulla, A. Arulmurugan, Improvement of test data compression using combined encoding, in International Conference on Electronics and Communication Systems (ICECS) (2015), pp. 635–638Google Scholar
  2. 2.
    S. Seo, Y. Lee, S. Kang, Tri-state coding using reconfiguration of twisted ring counter for test data compression. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 35(2), 274–284 (2016)CrossRefGoogle Scholar
  3. 3.
    J. Nicolai, Integrated circuit with mode detection pin for tristate level detection, U.S. Patent 5198707 (1993)Google Scholar
  4. 4.
    D. Thomson, P. Sheridan, J. Cleary, Tri-state input detection circuit. U.S. Patent: 6133753 (2000)Google Scholar
  5. 5.
    C.A. Chen, S.K. Gupta, Efficient BIST TPG design and test cube compaction via input reduction. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 17(8), 692–705 (2002)CrossRefGoogle Scholar
  6. 6.
    K.M. Butler, J. Saxena, A. Jain, T. Fryars, Minimizing power consumption in scan testing: pattern generation and DFT techniques, in International Conference on Test (2004), pp.355–364Google Scholar
  7. 7.
    A. Chandra, K. Chakrabarty, System-on-a-chip test-data compression and decompression architectures based on Golomb codes. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 20(3), 335–368 (2001)CrossRefGoogle Scholar
  8. 8.
    A. Chandra, K. Chakrabarty, Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans. Comput. 52(8), 1076–1088 (2003)CrossRefGoogle Scholar
  9. 9.
    P.T. Gonciari, B.M. Al-Hashimi, Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 22(6), 783–796 (2003)CrossRefGoogle Scholar
  10. 10.
    A.H. El-Maleh, Test data compression for system-on-a-chip using extended frequency-directed run-length (EFDR) code. IET Comput. Digit. Tech. 2(3), 155–163 (2008)CrossRefGoogle Scholar
  11. 11.
    T. Chen, X. Yi, W. Wang, J. Liu, H. Liang, F. Ren, Low power multistage test data compression scheme. Acta Electron. Sin. 45(6), 1384–1387 (2017)Google Scholar
  12. 12.
    K. Ji-shun, L. Jie-tang, Z. Liang, Test data compression method for multiple scan chain based on mirror-symmetrical reference slices. J. Electron. Inf. Technol. 37(6), 1514–1518 (2015)Google Scholar
  13. 13.
    K.A. Bhavsar, U.S. Mehta, Analysis of don’t care bits filling techniques for optimization of compression and scan power. Int. J. Comput. Appl. 18(3), 887–975 (2011)Google Scholar
  14. 14.
    W. Zhan, A. EL-Maleh, A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC), in International Conference on Computer Supported Cooperative Work in Design (2009), pp. 21–25Google Scholar
  15. 15.
    R. Sankaralingam, R.R. Oruganti, N.A. Touba, Static compaction techniques to control scan vector power dissipation, in Proceedings of IEEE VLSI Test Symposium (VTS) (2000), pp. 35–40Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Tian Chen
    • 1
    • 2
    Email author
  • Yongsheng Zuo
    • 1
    • 2
  • Xin An
    • 1
    • 2
  • Fuji Ren
    • 2
    • 3
    • 4
  1. 1.School of Computer and InformationHefei University of TechnologyHefeiChina
  2. 2.Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent MachineHefei University of TechnologyHefeiChina
  3. 3.School of Computer Science and Information EngineeringHefei University of TechnologyHefeiChina
  4. 4.Faculty of EngineeringThe University of TokushimaTokushimaJapan

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