Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs

  • Gökhan AkgünEmail author
  • Lester Kalms
  • Diana Göhringer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12083)


As FPGA devices become increasingly ubiquitous, the need for energy-conscious implementations for battery-powered devices arises. These new energy constraints have to be met in addition to the well-known area, latency and throughput requirements. Furthermore, the power dissipation of such systems is usually considered as a hardware problem. However, it can be solved effectively through hardware and software implementations of power-saving techniques. One generic energy-saving technique that does not require retroactive alteration of an HW/SW-design is dynamic voltage and frequency scaling (DVFS) which adjusts the power consumption and performance of an embedded device at run-time based on its workload and operating conditions. This work investigates the power monitoring and scaling capabilities of Xilinx Zynq-7000 SoCs and UltraScale+ MPSoCs. A real-time operating system (RTOS) manages the resources of an application, the voltage/frequency scaling and the power monitoring with its preemptive scheduling policies. Furthermore, the frequency is scaled without using additional hardware resources on the programmable logic from the processing system. The methodology can easily be used for changing the processor frequency at run-time. As a case study, we apply our technique to find energy-optimal voltage and frequency pairs for an image processing application designed using the open-source high-level synthesis library HiFlipVX. The proposed frequency scaling architecture requires up to 20% less flip-flops and look-up tables as compared to the same design with clocking wizard on the programmable logic.


Dynamic voltage and frequency scaling Image processing application HiFlipVX Frequency scaling without MMCM 



The work described in this paper has been supported in part by the German Federal Ministry of Education and Research BMBF (grant nr. 16KIS0663 SysKit_HW) and funded by the German Research Foundation (DFG, Deutsche Forschungsgemeinschaft) as part of Germany’s Excellence Strategy – EXC 2050/1 – Project ID 390696704 – Cluster of Excellence “Centre for Tactile Internet with Human-in-the-Loop” (CeTI) of Technische Universität Dresden.


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Gökhan Akgün
    • 1
    Email author
  • Lester Kalms
    • 1
  • Diana Göhringer
    • 1
    • 2
  1. 1.Adaptive Dynamic Systems, Technische Universität DresdenDresdenGermany
  2. 2.Centre for Tactile Internet with Human-in-the-loop (CeTi), Technische Universität DresdenDresdenGermany

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