Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study

  • Saurabh Jain
  • Longyang Lin
  • Massimo Alioto


This chapter introduces clock network reconfiguration for wide adaptation from nominal voltage down to deep sub-threshold voltages. Reconfiguration resolves the conflicting repeater insertion requirements at different voltages, in conventional static clock networks. In reconfigurable clock networks, the number of repeater levels is dynamically adapted to the supply voltage to ultimately mitigate the clock skew degradation across a wide voltage range. At nominal voltage, the number of repeater levels is adjusted to the highest value to mitigate the important clock skew contribution of wire delays. At lower voltages, the number of repeaters is progressively lowered to mitigate the increasingly dominant clock skew contribution of repeaters.


Reconfigurable clock network Wire delay Gate delay Bypassable repeater Clock repeater Clock tree Hold margin Robustness against hold violations Timing violations Minimum operating voltage Vmin Clock skew Launching register Capturing register Shallow clock network Deep clock network Monte Carlo simulations Clock skew standard deviation Histogram DIBL effect Clock distribution Clock signal Boostable clock repeater Clock root Clock sink Clock tree leaves Clock gater Dummy clock gater Bypassable clock gater Clock tree synthesis Automated clock tree design Level balance principle DVFS Fast Fourier Transform (FFT) Clock path replica Clock skew measurement Time-to-digital conversion Vernier delay line Above-threshold region Near-threshold region Sub-threshold region 


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Saurabh Jain
    • 1
  • Longyang Lin
    • 1
  • Massimo Alioto
    • 1
  1. 1.National University of SingaporeSingaporeSingapore

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