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Automated Design Flows and Run-Time Optimization for Reconfigurable Microarchitecures

  • Saurabh Jain
  • Longyang Lin
  • Massimo Alioto
Chapter
  • 32 Downloads

Abstract

In this chapter, a systematic methodology is introduced to design reconfigurable microarchitectures through automated and architecture-agnostic design flows. The main goal is to enrich a baseline microarchitecture with additional registers for throughput enhancement and then make selected registers bypassable to flexibly switch among different microarchitectures. Similarly, design methodologies for reconfigurable SRAM memories are described. As common thread, drop-in solutions for existing architectures allowing the above capability at very low design effort are discussed.

Keywords

Design methodology Digital design Design flow Gate-level netlist manipulation Automated synthesis and place&route CAD algorithm Reconfigurable microarchitecture Reconfigurable SRAM Pipestage-level reconfiguration Thread-level reconfiguration Bank-level reconfiguration Pipestage Pipeline stage Fan-out-of-4 delay Re-pipelining Register level Linear pipeline Feedforward pipeline Feedback pipeline Loop Register branch Dynamic energy Leakage energy Above-threshold region Near-threshold region Sub-threshold region Leakage-dynamic energy ratio Fixed microarchitectures Minimum energy point (MEP) Dynamically adaptable pipelines Dynamic voltage frequency scaling Power mode Bypassable register Bypassable flip-flop Non-bypassable register Non-bypassable flip-flop EDA tool Retiming Delay overhead Register bypassing Flip-flop bypassing Throughput enhancement Control flow Pipeline bubble Time-interleaved microarchitecture Time interleaving Input stream Instruction stream Channel Gate-level netlist SRAM Instruction memory Data memory Column multiplexing Column multiplexer Bitline Wordline Sense amplifier Precharge driver Write driver Bitcell Memory bank Memory sub-bank Reconfigurable array organization Access time Row aggregation Drop-in microarchitecture reconfiguration Electronic design automation (EDA) Pipeline stage unification AES Transparent register Static microarchitecture Dynamic microarchitecture Cycle-level timing Netlist Skeleton graph Register identification Bypassable register replacement Netlist-to-skeleton graph Graph weighting Level identification Cutset Feedforward cutset Cutset identification Cutset-to-pipeline mapping Even-numbered register identification Script Place&route (PNR) Behavioral RTL Register transfer level (RTL) Weighted skeleton graph Tcl script Cutset-based identification Non-linear pipelines Linear pipelines Register insertion Register merging Reconvergent path Branching path Graph Netlist graph Hash table Flip-flop reset Graph edge Graph node Dummy node Dummy edge Static timing analysis (STA) Weight Graph traversal Depth-first traversal Row decoder Reconfigurable decoder 

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Saurabh Jain
    • 1
  • Longyang Lin
    • 1
  • Massimo Alioto
    • 1
  1. 1.National University of SingaporeSingaporeSingapore

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