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Bitmap Index: A Processing-in-Memory Reconfigurable Implementation

  • M. Andrighetti
  • G. TurvaniEmail author
  • G. Santoro
  • M. Vacca
  • M. Ruo Roch
  • M. Graziano
  • M. Zamboni
Conference paper
  • 12 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 627)

Abstract

During the years, microprocessors went through impressive performance improvement thanks to technology development. CPUs became able to process great quantities of data. Memories also faced growth especially in density, but as far as speed is concerned the improvement did not proceed as the same rate. Processing-in-Memory (PIM) consists in enhancing the storage unit of a system, adding computing capabilities to memory cells, partially eliminating the need to transfer data from memory to execution unit. In this paper, a PIM architecture is presented for bulk bitwise operation mapped on the Bitmap Index application. The architecture is a memory array with logical computing abilities inside the cells. The array is a configurable modular architecture distributed in different banks, each bank is able to perform a different operation at the same time. This architecture has remarkable performance being faster than other solutions available in literature.

Keywords

Processing-in-memory Bitmap Index Reconfigurable architecture 

References

  1. 1.
    Angizi S, He Z, Fan D (2018 June) Pima-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation. In: 2018 55th ACM/ESDA/IEEE design automation conference (DAC), pp 1–6Google Scholar
  2. 2.
    Angizi S, He Z, Parveen F, Fan D (2017 July) Rimpa: a new reconfigurable dual-mode in-memory processing architecture with spin hall effect-driven domain wall motion device. In: 2017 IEEE Computer Society annual symposium on VLSI (ISVLSI), pp 45–50Google Scholar
  3. 3.
    Causapruno G, Riente F, Turvani G, Vacca M, Roch MR, Zamboni M, Graziano M (2016) Reconfigurable systolic array: from architecture to physical design for NML. IEEE Trans Very Large Scale Integr (VLSI) Syst (99):1–10Google Scholar
  4. 4.
    Chi P, Li S, Xu C, Zhang T, Zhao J, Liu Y, Wang Y, Xie Y (2016 June) Prime: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In: 2016 ACM/IEEE 43rd annual international symposium on computer architecture (ISCA), pp 27–39Google Scholar
  5. 5.
    Kim DH, Athikulwongse K, Healy MB, Hossain MM, Jung M, Khorosh I, Kumar G, Lee YJ, Lewis DL, Lin TW, Liu C, Panth S, Pathak M, Ren M, Shen G, Song T, Woo DH, Zhao X, Kim J, Choi H, Loh GH, Lee HHS, Lim SK (2015) Design and analysis of 3d-maps (3d massively parallel processor with stacked memory). IEEE Trans Comput 64(1):112–125MathSciNetCrossRefGoogle Scholar
  6. 6.
    Li S, Xu C, Zou Q, Zhao J, Lu Y, Xie Y (2016 June) Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. In: 2016 53nd ACM/EDAC/IEEE design automation conference (DAC), pp 1–6Google Scholar
  7. 7.
    Matsunaga S, Hayakawa J, Ikeda S, Miura K, Endoh T, Ohno H, Hanyu T (2009 Apr) MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. In: 2009 design, automation test in Europe conference exhibition, pp 433–435Google Scholar
  8. 8.
    Santoro G, Turvani G, Graziano M (2019) New logic-in-memory paradigms: an architectural and technological perspective. Micromachines 10(6). https://www.mdpi.com/2072-666X/10/6/368
  9. 9.
    Seshadri V, Lee D, Mullins T, Hassan H, Boroumand A, Kim J, Kozuch MA, Mutlu O, Gibbons PB, Mowry TC (2017) Ambit: In-memory accelerator for bulk bitwise operations using commodity dram technology. In: Proceedings of the 50th annual IEEE/ACM international symposium on microarchitecture, pp 273–287. MICRO-50 ’17, ACM, New York, NY, USA,  https://doi.org/10.1145/3123939.3124544
  10. 10.
    Zhang D, Jayasena N, Lyashevsky A, Greathouse JL, Xu L, Ignatowski M (2014) TOP-PIM: Throughput-oriented programmable processing in memory. In: Proceedings of the 23rd international symposium on high-performance parallel and distributed computing, pp 85–98. HPDC ’14, ACM, New York, NY, USA.  https://doi.org/10.1145/2600212.2600213

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • M. Andrighetti
    • 1
  • G. Turvani
    • 1
    Email author
  • G. Santoro
    • 1
  • M. Vacca
    • 1
  • M. Ruo Roch
    • 1
  • M. Graziano
    • 1
  • M. Zamboni
    • 1
  1. 1.Department of Electronics and TelecommunicationsPolitecnico di TorinoTurinItaly

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