A Simulink Model-Based Design of a Floating-Point Pipelined Accumulator with HDL Coder Compatibility for FPGA Implementation

  • Marco BassoliEmail author
  • Valentina Bianchi
  • Ilaria De Munari
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 627)


The design of an FPGA hardware architecture requires, traditionally, its description in a dedicated language (Hardware Description Language, HDL), which is often not well suited to manage wide and complex models. The design process can be simplified if the entire architecture can be described in a high abstraction level framework such as Simulink. In this paper a Simulink model-based design of a pipelined accumulator suitable for applications such as Support Vector Machine algorithms is presented. The compatibility with the HDL Coder workflow enables the direct FPGA model implementation. Moreover, the workflow output has been compared with a native VHDL equivalent floating-point accumulator intellectual property.


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Marco Bassoli
    • 1
    Email author
  • Valentina Bianchi
    • 1
  • Ilaria De Munari
    • 1
  1. 1.Department of Engineering and ArchitectureUniversity of ParmaParmaItaly

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