Trying to size a logic gate in isolation is a fruitless task. Making the gate larger will obviously reduce its external and total delay. But it will increase loading on the preceding stage. The aim of sizing should be to optimize the delay of a meaningful logic chain rather than a single gate. The best way to do this is by using logical effort. Logical effort assigns unitless numbers to gates which describe the normalized encumbrance they face by virtue of being “complicated”. This allows very powerful and versatile optimizations to be performed on entire logic chains. Logical effort techniques are invaluable in the design of complicated circuits, especially when large loads are observed. This is the case in critical circuitry such as power distribution, clock networks, pin drivers, and memory peripheral circuits.