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An Area Effective and High Speed SAR ADC Architecture for Wireless Communication

  • G. PrathibaEmail author
  • M. Santhi
Conference paper
  • 214 Downloads
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 44)

Abstract

An area effective, high speed and low power 8-bit Successive Approximation Register Analog to Digital converter (SAR-ADC) using 250 nm CMOS technology introduced in this paper. Among different types of ADC successive approximation is used as it is high speed architecture, suitable packed design and has good speed to power ratio. To minimize the power a Switched Inverter Quantization (SIQ) comparator and to reduce the leakage power the Multi Phase Clocking (MPC) based D-FF shift register for SAR logic are preferred for this work. The whole circuit design is bringing out with the help of Tanner EDA Tool.

Keywords

Area effective Low power High speed Speed to power ratio Tanner tool 

Abbreivations

SAR

Successive Approximation Register

ADC

Analog to Digital Converter

SIQ

Switched Inverter Quantization

MPC

Multi Phase Clocking

DAC

Digital to Analog Converter

Notes

Acknowledgments

Not applicable.

Author’s Contribution

G. Prathiba and M. Santhi are developed the main idea, designed a new architecture SAR-ADC using SIQ comparator and MPC based D-FF shift register. G.Prathiba construct and simulate the SIQ comparator, MPC based D-FF and SAR-ADC. M. Santhi reviewing the schematic, simulation output and Finalizing the manuscript. Authors are stuided and approved the completed manuscript.

Funding

This work does not have any funding.

Availability of Data and Materials.

Data sharing not applicable and no datasets were generated are analyzed.

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of ECEUniversity College of EngineeringAriyalurIndia
  2. 2.Department of ECESaranathan College of EngineeringTrichyIndia

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