Design Challenges for 3 Dimensional Network-on-Chip (NoC)

  • N. AshokKumarEmail author
  • P. Nagarajan
  • SathishKumar Selvaperumal
  • P. Venkatramana
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 39)


NoC (Network-on-Chip) is a technology is expected for resolve the problem of short imminence of buses. This technology approach is to design the information exchange between the subsystem of IP cores. The usage of common buses, which have the problem that they cannot scale in concern fixed and also the number of resources grows. NoC is proposed for resolving this short coming and especially implementing for switches/micro routers and resources in network strategy. The 3 Dimensional - NoC design paradigm is anticipated for ASIC design. The significant main impetus at the back move to 3D-NoC based arrangements is the deficiency of VLSI between chip correspondence plan strategy for the profound sub-micron chip producing innovation. Planning a proficient Network-on-Chip (NoC) engineering, while fulfilling the application execution imperatives is an intricate procedure. The outline issues traverse a few deliberation levels, going from abnormal state application displaying to physical design level execution. Probably the most critical stages in outlining the 3D-NoC include: Analyzing and portraying application activity. Combining the NoC topology for the application. Mapping and official of the centers with the NoC parts. Discovering ways for the activity streams and holding assets over the NoC. Picking 3D-NoC design parameters, for example, the information width of the connections, cradle sizes and recurrence of operation. Checking the outlined NoC for accuracy and execution.


3D NoC (3 Dimensional Network-on-Chip) TSV (Through Silicon Via) Topology Routing 


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • N. AshokKumar
    • 1
    Email author
  • P. Nagarajan
    • 1
  • SathishKumar Selvaperumal
    • 2
  • P. Venkatramana
    • 1
  1. 1.Centre for VLSI and Embedded Systems, Department of Electronics and Communication EngineeringSree Vidyanikethan Engineering CollegeTirupatiIndia
  2. 2.School of EngineeringAsia Pacific University of Technology and InnovationKuala LumpurMalaysia

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