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An Efficient Bridge Architecture for NoC Based Systems on FPGA Platform

  • S. P. GuruprasadEmail author
  • B. S. Chandrasekar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1084)

Abstract

The growing demands at the electronic consumer application areas have lent the requirement of embedded devices to be integrated on the same System on Chip (SoC). The SoC uses on-chip bus interconnection with shared memory communication. However, these buses are not scalable and limited to specific interface protocol. The Network on chip (NoC) provides a better interconnection solution for the SoC with reliable and scalable features. The bridge architecture is necessary to communicate the SoC through the NoC paradigm. Thus, the manuscript introduces an efficient bridge with Ethernet-Media Access Control (MAC) and also presented an interconnection of the bridge architecture having NoC based systems on targeted FPGA. The bridge architecture is consists of FIFO buffers, Serializer, priority based Arbiter, Credit counter Packet formation for Ethernet-MAC Transceiver module followed by packet parser and deserializer. The bridge with a single router and 2X2 NoC based systems are designed by using congestion free adaptive XY-routing. The proposed bridge architecture and the bridge with NoC are implemented over Artix-7 FPGA with prototyping. The performance analysis is considered in terms of Average latency, Maximum throughput at different packet injection rate for a bridge with NoC based systems.

Keywords

Bridge Ethernet-MAC FPGA NoC Network interface Router 

References

  1. 1.
    Jiang, S.: Rapid implementation of the MAC and interface circuits for the wireless LAN cards using FPGA. J. Commun. Netw. 1(3), 201–212 (1999)CrossRefGoogle Scholar
  2. 2.
    Elkeelany, O., Chaudhry, G.: A prototype of wideband/ethernet bridge using WEMAC. In: The 2002 45th Midwest Symposium on Circuits and Systems, 2002, MWSCAS-2002, vol. 1, p. I-595. IEEE (2002)Google Scholar
  3. 3.
    Kommineni, B.P., Srinivasan, R., Holsmark, R., Johansson, A., Kumar, S.: Modeling and Evaluation of a Network on Chip (NoC)–Internet Interface (2005)Google Scholar
  4. 4.
    Roopa, M.: Design of AMBA based AHB2APB bridge. IJCSNS 10(11), 14 (2010)Google Scholar
  5. 5.
    Nejad, A.B., Martinez, M.E., Goossens, K.: An FPGA bridge preserving traffic quality of service for on-chip network-based systems. In: 2011 Design, Automation & Test in Europe, pp. 1–6. IEEE (2011)Google Scholar
  6. 6.
    Michel, H., et al.: AMBA to SoCWire network on chip bridge as a backbone for a dynamic reconfigurable processing unit. In: 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego, CA, pp. 227–233 (2011)Google Scholar
  7. 7.
    Nejad, A.B., Molnos, A., Martinez, M.E., Goossens, K.: A hardware/software platform for QoS bridging over multi-chip NoC-based systems. Parallel Comput. 39(9), 424–441 (2013)CrossRefGoogle Scholar
  8. 8.
    Kyriakakis, E., Ngo, K., Öberg, J.: Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs. In: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of SoC, Linkoping, pp. 1–6 (2017)Google Scholar
  9. 9.
    Guruprasad, S.P., Chandrasekar, B.S.: An optimized packet transceiver design for ethernet-MAC layer based on FPGA. In: International Conference on Intelligent Data Communication Technologies and Internet of Things, pp. 725–732. Springer, Cham (2018)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of ECEJain UniversityBangaloreIndia
  2. 2.CDEVLJain UniversityBangaloreIndia

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