ADC in Broadband Communications

  • Fernando Gregorio
  • Gustavo González
  • Christian Schmidt
  • Juan Cousseau
Part of the Signals and Communication Technology book series (SCT)


Efficient and application-oriented analog-to-digital conversion (ADC) plays a key role on the performance of any communication system. Among the different available architectures, there exists a trade-off between sampling rate and resolution, both also related to the power consumption of the device. In addition, nonlinear distortion can severely reduce the digital dynamic range of the converted signal, thus reducing the effective resolution with the corresponding negative effect on the receiver sensitivity. In this sense, the selection and development of accurate models and compensation strategies are required to restore adequate performance. For example, the complexity of the models and compensation algorithms must also be considered in order to achieve an efficient solution. While ADCs used to sample narrowband signals have little memory effects and allow for simple models and compensation techniques, sampling of broadband signals introduces longer memory effects and more complex nonlinear dynamic models are required (Volterra, piece-wise linear models). Finally, adequate ADC performance metrics and figures of merit have to be carefully chosen to evaluate the quality of the compensation for the application at hand, as well as the measurement set-up and validation tests. In this chapter, we describe several of the available ADC architectures in terms of the achievable resolution and sampling rate, and the trade-off between them. Narrowband as well as wideband modeling and compensation techniques are described and proposed, depending on the particular ADC and the application at hand. Measurement related issues are also discussed.


  1. 1.
    R. Van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters (Kluwer Academic, Dordrecht, 2003)CrossRefGoogle Scholar
  2. 2.
    A. Buchwald, High-speed time interleaved ADCs. IEEE Commun. Mag. 54(4), 71–77 (2016)CrossRefGoogle Scholar
  3. 3.
    L.D. Vito, H. Lundin, S. Rapuano, Bayesian calibration of a lookup table for ADC error correction. IEEE Trans. Instrum. Meas. 56(3), 873–878 (2007)CrossRefGoogle Scholar
  4. 4.
    F.H. Irons, D.M. Hummels, S.P. Kennedy, Improved compensation for analog-to-digital converters. IEEE Trans. Circuits Syst. 38(8), 958–961 (1991)CrossRefGoogle Scholar
  5. 5.
    C. Huang, H. Ting, S. Chang, Analysis of nonideal behaviors based on INL/DNL plots for SAR ADCs. IEEE Trans. Instrum. Meas. 65(8), 1804–1817 (2016)CrossRefGoogle Scholar
  6. 6.
    S. Medawar, B. Murmann, P. H’́andel, N. Bj’́orsell, M. Jansson, Static integral nonlinearity modeling and calibration of measured and synthetic pipeline analog-to-digital converters. IEEE Trans. Instrum. Meas. 63(3), 502–511 (2014)CrossRefGoogle Scholar
  7. 7.
    N. Bjorsell, Modeling Analog to Digital Converters at Radio Frequency, Doctoral Thesis in Telecommunications, Stockholm, Sweden (2007)Google Scholar
  8. 8.
    ADSP-2148X, One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Analog Devices Inc. (2010)Google Scholar
  9. 9.
    H.F. Lundin, Characterization and Correction of Analog-to-digital Converters, Ph.D. Thesis, KTH, Stockholm, Sweden (2005)Google Scholar
  10. 10.
    S. Medawar, P. Handel, N. Bjorsell, M. Jansson, Postcorrection of pipelined analog-digital converters based on input-dependent integral nonlinearity modeling. IEEE Trans. Instrum. Meas. 60(10), 3342–3350 (2011)CrossRefGoogle Scholar
  11. 11.
    S. Ponnuru, M. Seo, U. Madhow, M. Rodwell, Joint mismatch and channel compensation for high-speed OFDM receivers with time-interleaved ADCs. IEEE Trans. Comm. 58(8), 2391–2401 (2010)CrossRefGoogle Scholar
  12. 12.
    P. Benabes, C. Lelandais-Perrault, N.L. Dortz, Mismatch calibration methods for high-speed time-interleaved ADCs, in 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS) (2014), pp. 49–52Google Scholar
  13. 13.
    C.A. Schmidt, J.E. Cousseau, J.L. Figueroa, B.T. Reyes, M.R. Hueda, Efficient estimation and correction of mismatch errors in time-interleaved ADCs. IEEE Trans. Instrum. Meas. 65(2), 243–254 (2016)CrossRefGoogle Scholar
  14. 14.
    C.A Schmidt, O. Lifschitz, J.E. Cousseau, J.L. Figueroa, P. Julian, Methodology and measurement setup for analog-to-digital converter postcompensation. IEEE Trans. Instrum. Meas. 63(3), 658–666 (2014)CrossRefGoogle Scholar
  15. 15.
    J. Elbornsson, F. Gustafsson, J. Eklund, Blind equalization of time errors in a time-interleaved ADC system. IEEE Trans. Signal Process. 53(4), 1413–1424 (2005)MathSciNetCrossRefGoogle Scholar
  16. 16.
    Y. Qiu, Y.J. Liu, J. Zhou, G. Zhang, D. Chen, N. Du, All-digital blind background calibration technique for any channel time-interleaved ADC. IEEE Trans. Circuits Syst. Regul. Pap. PP(99), 1–12 (2018)Google Scholar
  17. 17.
    C. Schmidt, J.E. Cousseau, J.L. Figueroa, R. Wichman, S. Werner, Characterization and compensation of nonlinearities in a continuous-time first-order ADC, in 2010 IEEE International Microwave Workshop Series on RF Front-ends for Software Defined and Cognitive Radio Solutions (IMWS) (2010), pp. 1–4Google Scholar
  18. 18.
    C.A. Schmidt, J.E. Cousseau, J.L. Figueroa, R. Wichman, S. Werner, Non-linearities modelling and post-compensation in continuous-time σδ modulators. IET Microwaves Antennas Propag.5(15), 1796–1804 (2011)CrossRefGoogle Scholar
  19. 19.
    C.A. Schmidt, J.L. Figueroa, J.E. Cousseau, A.M. Tonello, Pilot-based TI-ADC mismatch error calibration for IR-UWB receivers. IEEE Access 7, 74340–74350 (2019)CrossRefGoogle Scholar
  20. 20.
    M. Schetzen, The Volterra and Wiener theories of Nonlinear Systems (John Wiley and Sons Inc., New York, 1980)zbMATHGoogle Scholar
  21. 21.
    F.J. Doyle, R.K. Pearson, Identification and Control Using Volterra Models (Springer, London, 2002)CrossRefGoogle Scholar
  22. 22.
    S. Boyd, L.O. Chua, Fading memory and the problem of approximating nonlinear operators with Volterra series. IEEE Trans. Circuits Syst. 32(11), 1150–1161 (1985)MathSciNetCrossRefGoogle Scholar
  23. 23.
    I. Ryan, H. Mahdi, An oversampled rate converter using sigma delta noise shaping, in IET Irish Signals and Systems Conference, Dublin (2009), pp. 1–6Google Scholar
  24. 24.
    E. Bonizzoni, A.P. Perez, F. Maloberti, M. Garcia-Andrade, Third-order σ − δ modulator with 61-db SNR and 6-MHz bandwidth consuming 6 mW, in 34th European Solid-State Circuits Conference, Edinburgh (2008), pp. 218–221Google Scholar
  25. 25.
    T-S. Jeong, W. Choi, J. Gi, C. Yoo, Low voltage analog digital converter using sigma-delta modulator, in International SoC Design Conference, Busan (2008), pp. III52–III53Google Scholar
  26. 26.
    W-L. Yang, W-H. Hsieh, C-C. Hung, A third-order continuous-time sigma-delta modulator for Bluetooth, in International Symposium on VLSI Design, Automation and Test, Hsinchu (2009), pp. 247–250Google Scholar
  27. 27.
    A. Morgado, R. del Rio, J.M. de la Rosa, F. Medeiro, B. Perez-Verdu, F.V. Fernandez, A. Rodriguez-Vazquez, Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers, in IEEE International Symposium on Circuits and Systems, Island of Kos (2006), pp. 1884–1887Google Scholar
  28. 28.
    B.R. Jose, P. Mythili, J. Singh, J. Mathew, A triple-mode sigma-delta modulator design for wireless standards, in 10th International Conference on Information Technology, Orissa (2007), pp. 17–20Google Scholar
  29. 29.
    A. Leuciuc, On the nonlinearity of integrators in continuous-time delta-sigma modulators, in IEEE Midwest Symposium on Circuits and Systems, Dayton (2001), pp. 862–865Google Scholar
  30. 30.
    S. Pavan, Efficient simulation of weak nonlinearities in continuous-time oversampling converters. IEEE Trans. Circuits Syst. 57(8), 1925–1934 (2010)MathSciNetCrossRefGoogle Scholar
  31. 31.
    P. Sankar, S. Pavan, Analysis of integrator nonlinearity in a class of continuous-time delta-sigma modulators. IEEE Trans. Circuits Syst. 54(12), 1150–1161 (2007)CrossRefGoogle Scholar
  32. 32.
    T. Karema, T. Ritoniemi, H. Tenhunen, Intermodulation in sigma-delta D/A converters, in IEEE International Symposium on Circuits and Systems, Montreal (1991), pp. 1625–1628Google Scholar
  33. 33.
    M. Keramat, Functionality of quantization noise in sigma-delta modulators, in IEEE Midwest Symposium on Circuits and Systems, Lansing (2000), pp. 912–915Google Scholar
  34. 34.
    L. Samid, Y. Manoli, A multibit continuous time sigma delta modulator with successive-approximation quantizer, in IEEE International Symposium on Circuits and Systems, Island of Kos (2006), pp. 2965–2968Google Scholar
  35. 35.
    D.R. Morgan, Z. Ma, J. Kim, M.G. Zierdt, J. Pastalan, A generalized memory polynomial model for digital predistortion of RF power amplifiers. IEEE Trans. Circuits Syst. 54(10), 3852–3860 (2006)zbMATHGoogle Scholar
  36. 36.
    J.C. Gómez, E. Baeyens, Identification of block-oriented nonlinear systems using orthonormal bases. J. Process Control 14(6), 685–697 (2003)CrossRefGoogle Scholar
  37. 37.
    P. Nikaeen, B. Murmann, Digital compensation of dynamic acquisition errors at the front-end of high-performance A/D converters. IEEE J. Sel. Top. Sign. Proces. 3(3), 499–508 (2009)CrossRefGoogle Scholar
  38. 38.
    ADSP-2148X, One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Analog Devices Inc. (2010)Google Scholar
  39. 39.
    F. Centurelli, P. Monsurr, F. Rosato, D. Ruscio, A. Trifiletti, Calibration of pipeline ADC with pruned Volterra kernels. Electron. Lett. 52(16), 1370–1371 (2016)CrossRefGoogle Scholar
  40. 40.
    S.M.R. Islam, N. Avazov, O.A. Dobre, K.S. Kwak, Power-domain non-orthogonal multiple access (NOMA) in 5G systems: potentials and challenges. IEEE Commun. Surv. Tutorials PP(99), 1–1 (2016)Google Scholar
  41. 41.
    B.T. Reyes, R.M. Sanchez, A.L. Pola, M.R. Hueda, Design and experimental evaluation of a time-interleaved ADC calibration algorithm for application in high-speed communication systems. IEEE Trans. Circuits Syst. Regul. Pap. 64(5), 1019–1030 (2017)CrossRefGoogle Scholar
  42. 42.
    C.R. Anderson, S. Venkatesh, J.E. Ibrahim, R.M. Buehrer, J.H. Reed, Analysis and implementation of a time-interleaved ADC array for a software-defined UWB receiver. IEEE Trans. Veh. Technol. 58(8), 4046–4063 (2009)CrossRefGoogle Scholar
  43. 43.
    V.T.D. Huynh, N. Noels, H. Steendam, Offset mismatch calibration for TI-ADCs in high-speed OFDM systems, in 2015 IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT) (2015), pp. 1–5Google Scholar
  44. 44.
    S.K. Sindhi, K.M.M. Prabhu, Reconstruction of N-th order nonuniformly sampled bandlimited signals using digital filter banks. Digital Signal Process. 23, 1877–1886 (2013)CrossRefGoogle Scholar
  45. 45.
    J. Elbornsson, F. Gustafsson, J.E. Eklund, Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system. IEEE Trans. Circuits Syst. Regul. Pap. 51(1), 151–158 (2004)CrossRefGoogle Scholar
  46. 46.
    C. Vogel, H. Johansson, Time-interleaved analog-to-digital converters: status and future directions, in 2006 Proceedings of IEEE International Symposium on Circuits and Systems, 2006. ISCAS 2006 (2006), 3386–3389Google Scholar
  47. 47.
    C. Vogel, M. Hotz, S. Saleem, K. Hausmair, M. Soudan, A review on low-complexity structures and algorithms for the correction of mismatch errors in time-interleaved ADCs, in 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS) (2012), pp. 349–352Google Scholar
  48. 48.
    S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A.C. Carusone, All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(9), 2552–2560 (2017)CrossRefGoogle Scholar
  49. 49.
    S. Kwon, S. Lee, J. Kim, A joint timing synchronization, channel estimation, and SFD detection for IR-UWB systems. J. Commun. Networks 14(5), 501–509 (2012)CrossRefGoogle Scholar
  50. 50.
    P.P. Vaidyanathan, Multirate Systems and Filter Banks (Prentice Hall PTR, Englewood Cliffs, 1993)Google Scholar
  51. 51.
    T.I. Laakso, V. Valimaki, M. Karjalainen, U.K. Laine, Splitting the unit delay [FIR/all pass filters design]. IEEE Signal Process. Mag. 13(1), 30–60 (1996)CrossRefGoogle Scholar
  52. 52.
    G. Qin, G. Liu, M. Gao, X. Fu, P. Xu, Correction of sample-time error for time-interleaved sampling system using cubic spline interpolation. Metrol. Measur. Syst. 21(3), 485–496 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Fernando Gregorio
    • 1
  • Gustavo González
    • 1
  • Christian Schmidt
    • 1
  • Juan Cousseau
    • 1
  1. 1.Dpto. de Ing. Eléctrica y de Computadoras Universidad Nacional del Sur (UNS), Instituto de Inv. en Ing. Eléctrica “Alfredo Desages” (IIIE), UNS-CONICETBahía BlancaArgentina

Personalised recommendations