Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic

  • C. S. ManjuEmail author
  • N. Poovizhi
  • R. Rajkumar
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 35)


In today’s scenario modern electronic systems are in need of compact digital circuits. So, miniaturization of circuits is rapidly growing area. The speed and power consumption of a digital circuit is determined by Flip-flops. The total number of transistors in the clock generation circuit indirectly reduced by the introduction of the pass transistor logic in the existing flip flop design, which also reduces the power consumption of the circuit due to transistor reduction. Reduction of number of transistors in flip-flop design leads to miniaturization of digital circuits. In this paper, the pulse triggered Flip-Flop (FF) for power efficiency is designed and discussed. The AND function in the clock generation circuitry is replaced with the PTL based AND gate circuit. The n-mos transistors are arranged in parallel using the PTL based AND gate and due to faster discharge of the pulse less power is consumed.


Clock generation circuitry Digital circuits Flip-flops PTL n-mos transistors 


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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of ECEDr. N.G.P. Institute of TechnologyCoimbatoreIndia

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