Advertisement

Fault Tolerant Arithmetic Logic Unit

  • Shaveta ThakralEmail author
  • Dipali Bansal
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 35)

Abstract

Low power design is most challenging in this era of IC technology and shaken the Moore’s law. Various techniques have been invented for low power design and researchers are taking lot of pain to investigate new steps and methods to achieve low power goal. Reversible logic is seeking attention from last one decade and can be employed to balance between power and performance. Reversible logic is based on principle of no bit loss and claims almost no power dissipation. Although paradigm shifts from conventional logic to reversible logic is tedious but there is no other way looking around to reduce power dissipation. Many Reversible logic based arithmetic and logic units are available in literature but incorporating fault tolerance is demand of various applications. This paper aims in designing fault tolerant arithmetic logic unit based on high functionality conservative and parity preserving logic based gates. The quantum cost of used gates in proposed design is verified using RCViewer+ tool and performance of proposed design is evaluated with respect to existing designs in literature.

Keywords

Low power IC Reversible logic ALU Fault tolerant 

References

  1. 1.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183–191 (1961)MathSciNetCrossRefGoogle Scholar
  2. 2.
    Bennett, C.: Logical reversibility of computation. IBM J. Res. Dev. 17, 525–532 (1973)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Syamala, Y., Tilak, A.: Reversible arithmetic logic unit. In: 3rd International Conference Electronics Computer Technology (ICECT), pp 207–211. IEEE (2011)Google Scholar
  4. 4.
    Morrison, M., Lewandowski, M., Meana, R., Ranganathan, N.: Design of a novel reversible ALU using an enhanced carry lookahead adder. In: 2011 11th IEEE International Conference on Nanotechnology, pp 1436–1440. IEEE, Portland (2011)Google Scholar
  5. 5.
    Singh, R., Upadhyay, S., Jagannath, K., Hariprasad, S.: Efficient design of arithmetic logic unit using reversible logic gates. Int. J. Adv. Res. Comput. Eng. Technol. (IJARCET) 3(4) (2014)Google Scholar
  6. 6.
    Guan, Z., Li, W., Ding, W., Hang, Y., Ni, L.: An arithmetic logic unit design based on reversible logic gates. In: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim), pp 925–931. IEEE (2011)Google Scholar
  7. 7.
    Gupta, A., Malviya, U., Kapse, V.: Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors. In: NUiCONE, pp 1–6. IEEE (2012)Google Scholar
  8. 8.
    Saligram, R., Hegde, S.S., Kulkarni, S.A., Bhagyalakshmi, H.R., Venkatesha, M.K.: Design of parity preserving logic based fault tolerant reversible arithmetic logic unit. Int. J. VLSI Des. Commun. Syst. 4, 53–68 (2013)CrossRefGoogle Scholar
  9. 9.
    Bashiri, R., Haghparast, M.: Designing a novel nanometric parity preserving reversible ALU. J. Basic Appl. Sci. Res. 3, 572–580 (2013)Google Scholar
  10. 10.
    Moallem, P., Ehsanpour, M., Bolhasani, A., Montazeri, M.: Optimized reversible arithmetic logic units. J. Electron. 31, 394–405 (2014)Google Scholar
  11. 11.
    Gopal, L., Syahira, N., Mahayadin, M., Chowdhury, A., Gopalai, A., Singh, A.: Design and synthesis of reversible arithmetic and logic unit (ALU). In: International Conference on Computer, Communications, and Control Technology (I4CT), pp 289–293. IEEE (2014)Google Scholar
  12. 12.
    Sen, B., Dutta, M., Goswami, M., Sikdar, B.: Modular design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectron. J. 45, 1522–1532 (2014)CrossRefGoogle Scholar
  13. 13.
    Thakral, S., Bansal, D.: Fault tolerant ALU using parity preserving reversible logic gates. Int. J. Mod. Educ. Comput. Sci. 8, 51–58 (2016)CrossRefGoogle Scholar
  14. 14.
    Sasamal, T., Singh, A., Mohan, A.: Efficient design of reversible ALU in quantum-dot cellular automata. Optik 127, 6172–6182 (2016)CrossRefGoogle Scholar
  15. 15.
    Krishna Murthy, M.: Design of efficient adder circuits using proposed parity preserving gate (PPPG). Int. J. VLSI Des. Commun. Syst. 3, 83–939 (2012)CrossRefGoogle Scholar
  16. 16.
    Thakral, S., Bansal, D., Chakarvarti, S.: Implementation and analysis of reversible logic based arithmetic logic unit. TELKOMNIKA (Telecommun. Comput. Electron. Control) 14, 1292 (2016)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of Electronics and Communication (FET)Manav Rachna International Institute of Research and StudiesFaridabadIndia

Personalised recommendations