SIRM: Shift Insensitive Racetrack Main Memory

  • Hongbin Zhang
  • Bo Wei
  • Youyou Lu
  • Jiwu ShuEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11783)


Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.


Racetrack memory Shift insensitive Main memory 


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Copyright information

© IFIP International Federation for Information Processing 2019

Authors and Affiliations

  1. 1.Tsinghua UniversityBeijingChina
  2. 2.Hangzhou Dianzi UniversityHangzhouChina

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