KLSAT: An Application Mapping Algorithm Based on Kernighan–Lin Partition and Simulated Annealing for a Specific WK-Recursive NoC Architecture

  • XiaoJun WangEmail author
  • Feng ShiEmail author
  • Hong ZhangEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11783)


Application mapping is a critical phase in NoC design because of the running time, the network latency and the power consumption. In order to reduce these problems of applications running on multicore architecture, we propose a novel application mapping algorithm, called KLSAT mapping algorithm. It is used for the triplet-based architecture (TriBA) topology which is WK-recursive based networks well conform to a modular design due to the properties of regularity and scalability. The KLSAT mapping algorithm exploits the advantage of both the Kernighan–Lin partitioning algorithm and simulated annealing algorithm to reduce the overall power consumption and network latency. Compared to the random mapping algorithm, the experiment results reveal that the solutions generated by the proposed mapping algorithm reduce average power consumption and network latency by 6.4%, 12.2% in mapping 27 cores and 29.5%, 26.7% in mapping 81 cores respectively.


WK-recursive network Kernighan–Lin algorithm Simulated annealing algorithm Application mapping Network-on-Chip 


  1. 1.
    Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: DAC 2001, pp. 684–689, June 2001Google Scholar
  2. 2.
    Benini, L., Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Trans. Comput. 35(1), 70–78 (2002)Google Scholar
  3. 3.
    Farahabady, M., Sarbazi-Azad, H.: The WK-recursive pyramid: an efficient network topology. In: PAAN 2005, pp. 6–11, December 2005Google Scholar
  4. 4.
    Wang, Y., Juan, S.: Hamiltonicity of the basic WK-recursive pyramid with and without faulty nodes. J. Theor. Comput. Sci. 562(C), 542–556 (2015)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Taylor, M.B., Lee, W., Miller, J., et al.: Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams. ACM SIGARCH Comput. Archit. News 32(2), 2–13 (2004)CrossRefGoogle Scholar
  6. 6.
    Hoskote, Y., Vangal, S., et al.: A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5), 51–61 (2007)CrossRefGoogle Scholar
  7. 7.
    Shi, F., Ji, W., et al.: A triplet-based computer architecture supporting parallel object computing. In: IEEE ASSAP 2007, pp. 192–197, July 2007Google Scholar
  8. 8.
    Sahu, P., Manna, N., Shah, N., Chattopadhyay, S.: Extending Kernighan-Lin partitioning heuristic for application mapping onto network-on-chip. J. Syst. Archit. 60(7), 562–578 (2014)CrossRefGoogle Scholar
  9. 9.
    Zhu, D., Chen, L., Yue, S., Pedram, M.: Application mapping for express channel-based networks-on-chip. In: DATE 2014, pp. 1–6, March 2014Google Scholar
  10. 10.
    Manna, K., Choubey, V., et al.: Thermal variance-aware application mapping for mesh based network-on-chip design using Kernighan-Lin partitioning. In: PDGC 2014, pp. 274–279. IEEE, December 2014Google Scholar
  11. 11.
    Fang, J., Yu, L., et al.: KLGA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design. J. Supercomputing 71(11), 4056–4071 (2015)MathSciNetCrossRefGoogle Scholar
  12. 12.
    Manna, K., Teja, V., Chattopadhyay, S., et al.: TSV placement and core mapping for 3D mesh based network-on-chip design using extended Kernighan-Lin Partitioning. In: VLSI 2015, pp. 392–397. IEEE, July 2015Google Scholar
  13. 13.
    Hu, J., Marculescu, R.: Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), 551–562 (2005)CrossRefGoogle Scholar
  14. 14.
    Marcon, C., Moreno, E., Calazans, L., Moraes, F.: Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2(6), 471–482 (2008)CrossRefGoogle Scholar
  15. 15.
    Prasad, N., Mukherjee, P., Chattopadhyay, S., et al.: Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parall. Distrib. Comput. 113(2), 17–36 (2018)CrossRefGoogle Scholar
  16. 16.
    Dong, Z., Yang, B., Hu, P., et al.: An efficient global energy optimization approach for robust 3D plane segmentation of point clouds. ISPRS J. Photogra. Remote Sens. 137(1), 112–133 (2018)CrossRefGoogle Scholar
  17. 17.
    Orsila, H., Salminen, E., Timo, D.: Best practices for simulated annealing in multiprocessor task distribution problems. Tech. 4(2), 197–198 (2008)Google Scholar
  18. 18.
    Yang, B., Liang, G., et al.: Parameter-optimized simulated annealing for application mapping on networks-on-chip. In: LIO 2012, pp. 307–322 (2012)Google Scholar
  19. 19.
    Tosun, S., Ozturk, O., Ozkan, E., Ozen, M.: Application mapping algorithms for mesh-based network-on-chip architectures. J. Supercomputing 71(3), 995–1017 (2015)CrossRefGoogle Scholar
  20. 20.
    Cheng, C., Chen, W.: Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms. J. Supercomputing 72(11), 1–14 (2016)CrossRefGoogle Scholar
  21. 21.
    Zhong, L., Sheng, J., et al.: An optimized mapping algorithm based on simulated annealing for regular NoC architecture. In: ASIC 2011, pp. 389–392. IEEE, October 2011Google Scholar
  22. 22.
    Larsson, T., Jesper, F.: Direct graph k-partitioning with a Kernighan-Lin like heuristic. Oper. Res. Lett. 34(6), 621–629 (2006)MathSciNetCrossRefGoogle Scholar
  23. 23.
    Ye, T., Benini, L., Micheli, G.: Analysis of power consumption on switch fabrics in network routers. In: DAC 2002, pp. 524–529, June 2002Google Scholar
  24. 24.
    Hu, J., Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: ASPDAC 2003, pp. 233–239. IEEE (2003)Google Scholar
  25. 25.
    Kahng, A., Li, B., Peh, L., Samadi, K.: ORION 2.0: a power-area simulator for interconnection networks. IEEE Trans. Very Large Scale Integr. Syst. 20(1), 191–196 (2012)CrossRefGoogle Scholar
  26. 26.
    Bienia, C., Li, K.: PARSEC 2.0: a new benchmark suite for chip-multiprocessors. In: AWMBS 2009, pp. 1–9. IEEE (2009)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2019

Authors and Affiliations

  1. 1.Beijing Institute of TechnologyBeijingChina
  2. 2.Henan University of Economics and LawZhengzhouChina

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