High Throughput VLSI Architectures for CRC-12 Computation

  • R. Ashok Chaitanya VarmaEmail author
  • M. Venkata SubbaraoEmail author
  • G. R. L. V. N. Srinivasa RajuEmail author
Conference paper
Part of the Learning and Analytics in Intelligent Systems book series (LAIS, volume 3)


This paper presents high speed VLSI architectures from serial architectures to parallel architectures with improved throughput and low latency. This paper introduces IIR filter based design architecture for implementation of parallel CRC and comparison is done for the implementations of CRC-12 polynomial equation. A LFSR is used as main component for these implementations. The proposed design consists of parallel architectures of Single and multi level. These architectures had been implemented using verilog language code and simulated using Xilinx tool 14.1.


CRC LFSR Look ahead approach IIR filter design 


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Department of ECEShri Vishnu Engineering College for WomenBhimavaramIndia

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