SOC Design Verification

  • Veena S. Chakravarthi


This chapter deals with the importance of SOC design verification, plan and strategies adopted for verification. It defines functional simulation, functional coverage, code coverage, and other important terms used in verification. Importance of FPGA validation and how it complements the SOC design verification is explained in this chapter. Most of the simulation concept of SOC design verification explained in the chapter can be seen in the verification of the reference designs provided in Chapter 12.


Simulation VIP Test bench SOC under test Test environment Test script Regression Run script Bug tracking Verification tools NCSim Vera SystemVerilog DUT Bug-debug Bug fix 


  1. 1.
    SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Chris SpearGoogle Scholar
  2. 2.
    Writing Testbenches using System Verilog, Bergeron, JanickGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Veena S. Chakravarthi
    • 1
  1. 1.Sensesemi Technologies Private LimitedBangaloreIndia

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