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SOC Design for Testability (DFT)

  • Veena S. Chakravarthi
Chapter

Abstract

This chapter describes requirement for testability, the design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC design in the context of DFT. This chapter introduces the concept of compression and need for test optimization to reduce ATE test times and its impact on economics of SOC.

Keywords

DFT mode LBIST PMBIST Boundary scan JTAG IEEE 1149.1/6 ATPG MISR PRPG Scan compression 

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Veena S. Chakravarthi
    • 1
  1. 1.Sensesemi Technologies Private LimitedBangaloreIndia

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