Axonal Delay Controller for Spiking Neural Networks Based on FPGA
In this paper, the implementation of a programmable Axonal Delay Controller (ADyC) mapped on a hardware Neural Processor (NP) FPGA-based is reported. It is possible to define axonal delays between 1 to 31 emulation cycles to global and local pre-synaptic spikes generated by NP, extending the temporal characteristics supported by this architecture. The prototype presented in this work contributes to the realism of the network, which mimics the temporal biological characteristics of spike propagation through the cortex. The contribution of temporal information is strongly related to the learning process. ADyC operation is transparent for the rest of the system and neither affects the remaining tasks executed by the NP nor the emulation time period. In addition, an example implemented on hardware of a neural oscillator with programmable delays configured for a set of neurons is presented in order to demonstrate full platform functionality and operability.
KeywordsAxonal delay FPGA Spiking Neural Networks
This work has been partially funded by the Spanish Ministry of Science and Innovation and the European Social Fund (ESF) under Projects TEC2011-27047 and TEC2015-67278-R. Mireya Zapata held a scholarship from National Secretary of High Education, Science, Technology, and Innovation (SENESCYT) of the Ecuadorian government.
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