Advertisement

Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications

  • Xinfei Guo
  • Mircea R. Stan
Chapter

Abstract

The advent of FinFETs has extended the CMOS lifeline by a few more technology nodes (5 nm and even 3 nm are now under development), so it is critical for digital circuit designers and researchers to understand some of the fundamental differences between advanced FinFET nodes and older planar devices, along with the associated challenges (e.g., design and aging challenges) in the forthcoming sub-10 nm regime. This chapter consists of two major thrusts. In the first thrust, we present a comprehensive study that compares multiple technology nodes spanning from old planar devices to the most advanced FinFET nodes. This study adds to the FinFET design knowledge base and helps designers gain a thorough understanding of various design challenges. The second trust mainly looks at the impact of FinFET aging within the context of Internet of Things (IoT). Through extensive simulations with foundry-provided FinFET aging models, we conclude that aging can severely affect certain category of IoT applications; hence, this aspect needs to be incorporated in the design cycle to meet the overall system lifetime targets. Several candidate techniques against aging are also presented for designing robust IoT chips that perform faster, consume lower power, and last longer than without the use of these techniques.

Keywords

FinFETs FDSOI VLSI Scaling Digital design IoT BTI HCI Lifetime Sleep mode Recovery 

References

  1. 1.
    Gordon E Moore. Cramming more components onto integrated circuits. Proceedings of the IEEE, 86(1):82–85, 1998.MathSciNetCrossRefGoogle Scholar
  2. 2.
    Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, William Yee Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent Carlton, et al. A 2.4 GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. In Solid-State Circuits Conference (ISSCC), 2017 IEEE International, pages 226–227. IEEE, 2017.Google Scholar
  3. 3.
    Debajit Bhattacharya and Niraj K Jha. FinFETs: From Devices to Architectures. Advances in Electronics, 2014, 2014.Google Scholar
  4. 4.
    Benton H Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T Pileggi, Rob A Rutenbar, and Kenneth L Shepard. Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proceedings of the IEEE, 96(2):343–365, 2008.CrossRefGoogle Scholar
  5. 5.
    James Warnock. Circuit Design Challenges at the 14nm Technology Node. In Proceedings of the 48th Design Automation Conference, pages 464–467. ACM, 2011.Google Scholar
  6. 6.
    Robert Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, and Vikas Chandra. Physical Design and FinFETs. In Proceedings of the 2014 on International symposium on physical design, pages 65–68. ACM, 2014.Google Scholar
  7. 7.
    Jong-Ho Lee. Bulk FinFETs: Design at 14 nm Node and Key Characteristics. In Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, pages 33–64. Springer, 2016.Google Scholar
  8. 8.
    Bin Yu, Leland Chang, Shibly Ahmed, Haihong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery, Chau Ho, Qi Xiang, Tsu-Jae King, et al. FinFET Scaling to 10 nm Gate Length. In Electron Devices Meeting, 2002. IEDM’02. International, pages 251–254. IEEE, 2002.Google Scholar
  9. 9.
    Jamil Kawa. Designing with FinFETs: The Opportunities and the Challenges. In Synopsys White Paper, pages 1–8. Synopsys, 2012.Google Scholar
  10. 10.
    Lawrence T Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, and Greg Yeric. ASAP7: A 7-nm FinFET Predictive Process Design Kit. Microelectronics Journal, 53:105–115, 2016.CrossRefGoogle Scholar
  11. 11.
    Prateek Mishra, Anish Muttreja, and Niraj K Jha. FinFET Circuit Design. In Nanoelectronic Circuit Design, pages 23–54. Springer, 2011.Google Scholar
  12. 12.
    Anish Muttreja, Niket Agarwal, and Niraj K Jha. CMOS Logic Design with Independent-gate FinFETs. In Computer Design, 2007. ICCD 2007. 25th International Conference on, pages 560–567. IEEE, 2007.Google Scholar
  13. 13.
    Farhana Sheikh and Vidya Varadarajan. The Impact of Device-width Quantization on Digital Circuit Design Using FinFET Structures. Proc. EE241 Spring, 1, 2004.Google Scholar
  14. 14.
    Jie Gu, John Keane, Sachin Sapatnekar, and Chris Kim. Width Quantization Aware FinFET Circuit Design. In Custom Integrated Circuits Conference, 2006. CICC’06. IEEE, pages 337–340. IEEE, 2006.Google Scholar
  15. 15.
    Wen-Kuan Yeh, Wenqi Zhang, Yi-Lin Yang, An-Ni Dai, Kehuey Wu, Tung-Huan Chou, Cheng-Li Lin, Kwang-Jow Gan, Chia-Hung Shih, and Po-Ying Chen. The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET. IEEE Transactions on Device and Materials Reliability, 16(4):610–616, 2016.CrossRefGoogle Scholar
  16. 16.
    Brian Swahn and Soha Hassoun. Gate Sizing: FinFETs vs 32nm Bulk MOSFETs. In Design Automation Conference, 2006 43rd ACM/IEEE, pages 528–531. IEEE, 2006.Google Scholar
  17. 17.
    Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, and Feng Yuan. FinFETs With Different Fin Heights, August 23 2016. US Patent 9,425,102.Google Scholar
  18. 18.
    Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu-Ting Zhang, Shang-Rong Fang, Santanu Santra, and Rung-Bin Lin. Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. In VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pages 673–678. IEEE, 2016.Google Scholar
  19. 19.
  20. 20.
    Huajie Zhou, Yi Song, Qiuxia Xu, Yongliang Li, and Huaxiang Yin. Fabrication of Bulk-Si FinFET Using CMOS Compatible Process. Microelectronic Engineering, 94:26–28, 2012.CrossRefGoogle Scholar
  21. 21.
    M-S Kim, Tom Vandeweyer, Efrain Altamirano-Sanchez, Harold Dekkers, Els Van Besien, Diana Tsvetanova, Olivier Richard, S Chew, Guillaume Boccardi, and Naoto Horiguchi. Self-aligned double patterning of 1× nm finfets; a new device integration through the challenging geometry. In Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on, pages 101–104. IEEE, 2013.Google Scholar
  22. 22.
    FinFET, Multi-Patterning Aware Place, and Route Implementation:. http://go.mentor.com/4h_c2.
  23. 23.
    Mastering the Magic of Multi-Patterning:. http://go.mentor.com/4gue4.
  24. 24.
    Yongxun Liu, Kenichi Ishii, Meishoku Masahara, Toshiyuki Tsutsumi, Hidenori Takashima, Hiromi Yamauchi, and Eiichi Suzuki. Cross-sectional Channel Shape Dependence of Short-channel Effects in Fin-type Double-gate Metal Oxide Semiconductor Field-effect Transistors. Japanese journal of applied physics, 43(4S):2151, 2004.CrossRefGoogle Scholar
  25. 25.
    W. P. Maszara and M. R. Lin. FinFETs - Technology and Circuit Design Challenges. In 2013 Proceedings of the ESSCIRC (ESSCIRC), pages 3–8, Sept 2013.Google Scholar
  26. 26.
    Brad D Gaynor and Soha Hassoun. Fin Shape Impact on FinFET Leakage with Application to Multithreshold and Ultralow-leakage FinFET design. IEEE Transactions on Electron Devices, 61(8):2738–2744, 2014.CrossRefGoogle Scholar
  27. 27.
    Andy Biddle and Jason ST Chen. FinFET Technology-Understanding and Productizing a New Transistor. A joint whitepaper from TSMC and Synopsys, 2013.Google Scholar
  28. 28.
    M Rashed, N Jain, J Kim, M Tarabbia, I Rahim, S Ahmed, Je Kim, I Lin, S Chan, H Yoshida, et al. Innovations in Special Constructs for Standard Cell Libraries in Sub 28nm Technologies. In Electron Devices Meeting (IEDM), 2013 IEEE International, pages 9–7. IEEE, 2013.Google Scholar
  29. 29.
    Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, and H-S Philip Wong. 32-bit Processor Core at 5-nm Technology: Analysis of Transistor and Interconnect Impact on VLSI System Performance. In Electron Devices Meeting (IEDM), 2016 IEEE International, pages 28–3. IEEE, 2016.Google Scholar
  30. 30.
  31. 31.
    Silvestre Salas Rodriguez, Julio C Tinoco, Andrea G Martinez-Lopez, Joaquín Alvarado, and Jean-Pierre Raskin. Parasitic Gate Capacitance Model for Triple-gate FinFETs. IEEE Transactions on Electron Devices, 60(11):3710–3717, 2013.CrossRefGoogle Scholar
  32. 32.
    Ning Lu, Terence B Hook, Jeffrey B Johnson, Carl Wermer, Christopher Putnam, and Richard A Wachnik. Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements. IEEE Electron Device Letters, 34(9):1100–1102, 2013.CrossRefGoogle Scholar
  33. 33.
    C Calvin Hu. Modern Semiconductor Devices for Integrated Circuits. Part 7: MOSFETs in ICs – Scaling, Leakage, and Other Topics, 2011.Google Scholar
  34. 34.
    Pablo Royer, Paul Zuber, Binjie Cheng, Asen Asenov, and Marisa Lopez-Vallejo. Circuit-level Modeling of FinFET Sub-threshold Slope and DIBL Mismatch Beyond 22nm. In Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on, pages 204–207. IEEE, 2013.Google Scholar
  35. 35.
    Pranita Kerber, Qintao Zhang, Siyuranga Koswatta, and Andres Bryant. GIDL in Doped and Undoped FinFET Devices for Low-leakage Applications. IEEE Electron Device Letters, 34(1):6–8, 2013.CrossRefGoogle Scholar
  36. 36.
    Seongjae Cho, Jung Hoon Lee, Shinichi O’uchi, Kazuhiko Endo, Meishoku Masahara, and Byung-Gook Park. Design of SOI FinFET on 32nm Technology Node for Low Standby Power (LSTP) Operation Considering Gate-induced Drain Leakage (GIDL). Solid-State Electronics, 54(10):1060–1065, 2010.Google Scholar
  37. 37.
    Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Michal Rakowski, Claude Ortolland, L-Å Ragnarsson, Bertrand Parvais, Ari De Keersgieter, Stefan Kubicek, et al. Benchmarking SOI and Bulk FinFET Alternatives for PLANAR CMOS Scaling Succession. Solid-State Electronics, 54(9):855–860, 2010.CrossRefGoogle Scholar
  38. 38.
    Neil HE Weste and David Money Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Addison-Wesley, 2005.Google Scholar
  39. 39.
    Takayasu Sakurai and A Richard Newton. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid-State Circuits, 25(2):584–594, 1990.CrossRefGoogle Scholar
  40. 40.
    James W Tschanz, James T Kao, Siva G Narendra, Raj Nair, Dimitri A Antoniadis, Anantha P Chandrakasan, and Vivek De. Adaptive Body Bias for Reducing Impacts of Die-to-die and Within-die Parameter Variations on Microprocessor Frequency and Leakage. IEEE Journal of Solid-State Circuits, 37(11):1396–1402, 2002.CrossRefGoogle Scholar
  41. 41.
    Wen-Teng Chang, Shih-Wei Lin, Cheng-Ting Shih, and Wen-Kuan Yeh. Back Bias Modulation of UTBB FDSOI, Bulk FinFET, and SOI FinFET. In Nanoelectronics Conference (INEC), 2016 IEEE International, pages 1–2. IEEE, 2016.Google Scholar
  42. 42.
    D. Burnett, S. Parihar, H. Ramamurthy, and S. Balasubramanian. Finfet sram design challenges. In 2014 IEEE International Conference on IC Design Technology, pages 1–4, May 2014.Google Scholar
  43. 43.
    Witek P Maszara. Finfets: Designing for new logic technology. In Micro-and Nanoelectronics: Emerging Device Challenges and Solutions, pages 113–136. CRC Press, 2014.Google Scholar
  44. 44.
    B. Zimmer, S. O. Toh, H. Vo, Y. Lee, O. Thomas, K. Asanovic, and B. Nikolic. Sram assist techniques for operation in a wide voltage range in 28-nm cmos. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12):853–857, Dec 2012.CrossRefGoogle Scholar
  45. 45.
    T. Song, W. Rim, S. Park, Y. Kim, G. Yang, H. Kim, S. Baek, J. Jung, B. Kwon, S. Cho, H. Jung, Y. Choo, and J. Choi. A 10 nm finfet 128 mb sram with assist adjustment system for power, performance, and area optimization. IEEE Journal of Solid-State Circuits, 52(1):240–249, Jan 2017.CrossRefGoogle Scholar
  46. 46.
    Woojoo Lee, Yanzhi Wang, Tiansong Cui, Shahin Nazarian, and Massoud Pedram. Dynamic Thermal Management for FinFET-based Circuits Exploiting the Temperature Effect Inversion Phenomenon. In Proceedings of the 2014 international symposium on Low power electronics and design, pages 105–110. ACM, 2014.Google Scholar
  47. 47.
    David Wolpert and Paul Ampadu. Temperature effects in semiconductors. In Managing temperature effects in nanoscale adaptive systems, pages 15–33. Springer, 2012.Google Scholar
  48. 48.
    Warin Sootkaneung, Sasithorn Chookaew, and Suppachai Howimanporn. Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance. In Asian Test Symposium (ATS), 2016 IEEE 25th, pages 310–315. IEEE, 2016.Google Scholar
  49. 49.
    Yazhou Zu, Wei Huang, Indrani Paul, and Vijay Janapa Reddi. Ti-states: Processor Power Management in the Temperature Inversion Region. In Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on, pages 1–13. IEEE, 2016.Google Scholar
  50. 50.
    Katayoun Neshatpour, Wayne Burleson, Amin Khajeh, and Houman Homayoun. Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.Google Scholar
  51. 51.
    Ermao Cai and Diana Marculescu. TEI-turbo: Temperature Effect Inversion-aware Turbo Boost for FinFET-based Multi-core Systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 500–507. IEEE Press, 2015.Google Scholar
  52. 52.
    Ermao Cai, Dimitrios Stamoulis, and Diana Marculescu. Exploring Aging Deceleration in FinFET-based Multi-core Systems. In Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on, pages 1–8. IEEE, 2016.Google Scholar
  53. 53.
    Emanuele Baravelli, Malgorzata Jurczak, Nicolò Speciale, Kristin De Meyer, and Abhisek Dixit. Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance. IEEE transactions on nanotechnology, 7(3):291–298, 2008.CrossRefGoogle Scholar
  54. 54.
    Xingsheng Wang, Andrew R Brown, Binjie Cheng, and Asen Asenov. Statistical Variability and Reliability in Nanoscale FinFETs. In Electron Devices Meeting (IEDM), 2011 IEEE International, pages 5–4. IEEE, 2011.Google Scholar
  55. 55.
    Shiva Taghipour and Rahebeh Niaraki Asli. Aging Comparative Analysis of High-performance FinFET and CMOS Flip-flops. Microelectronics Reliability, 69:52–59, 2017.CrossRefGoogle Scholar
  56. 56.
    Hai Jiang, SangHoon Shin, Xiaoyan Liu, Xing Zhang, and Muhammad Ashraful Alam. The Impact of Self-Heating on HCI Reliability in High-Performance Digital Circuits. IEEE Electron Device Letters, 38(4):430–433, 2017.CrossRefGoogle Scholar
  57. 57.
    Semiconductor Engineering Reliability Challenges In 16nm FinFET Design:. http://semiengineering.com/reliability-challenges-16nm-finfet-design/.
  58. 58.
    Mark LaPedus. Interconnect challenges rising: Resistance and capacitance drive need for new materials and approaches. http://semiengineering.com/interconnect-challenges-grow-3/, 2016.
  59. 59.
    Ning Lu and Richard A Wachnik. Modeling of Resistance in FinFET Local Interconnect. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(8):1899–1907, 2015.MathSciNetCrossRefGoogle Scholar
  60. 60.
    Spencer Tu. Putting the Pieces Together in the Materials Space: Advanced Materials Solutions for 10nm and Beyond. In SEMICON Taiwan, 2015.Google Scholar
  61. 61.
    Alice Wang, Anantha P Chandrakasan, and Stephen V Kosonocky. Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. In VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on, pages 7–11. IEEE, 2002.Google Scholar
  62. 62.
    Nathaniel Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G Dreslinski, Trevor Mudge, Dennis Sylvester, and David Blaauw. Near-threshold Computing in FinFET Technologies: Opportunities for Improved Voltage Scalability. In Proceedings of the 53rd Annual Design Automation Conference, page 76. ACM, 2016.Google Scholar
  63. 63.
    O Weber. FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications. In IC Design and Technology (ICICDT), 2017 IEEE International Conference on, pages 1–3. IEEE, 2017.Google Scholar
  64. 64.
    Dimitrios Serpanos and Marilyn Wolf. IoT Devices. In Internet-of-Things (IoT) Systems, pages 17–23. Springer, 2018.Google Scholar
  65. 65.
    Gopal Singh Jamnal, Xiaodong Liu, Lu Fan, and Muthu Ramachandran. Cognitive Internet of Everything (CIoE): State of the Art and Approaches. In Emerging Trends and Applications of the Internet of Things, pages 277–309. IGI Global, 2017.Google Scholar
  66. 66.
    Byungseok Kang, Daecheon Kim, and Hyunseung Choo. Internet of Everything: A large-scale autonomic IoT gateway. IEEE Transactions on Multi-Scale Computing Systems, 2017.Google Scholar
  67. 67.
    Massimo Alioto. Enabling the Internet of Things: From Integrated Circuits to Integrated Systems. Springer, 2017.CrossRefGoogle Scholar
  68. 68.
    Brian Bailey. Chip aging becomes design problem. Semiconductor Engineering, 2018.Google Scholar
  69. 69.
    James H Stathis, M Wang, RG Southwick, EY Wu, BP Linder, EG Liniger, G Bonilla, and H Kothari. Reliability challenges for the 10nm node and beyond. In Electron Devices Meeting (IEDM), 2014 IEEE International, pages 20–6. IEEE, 2014.Google Scholar
  70. 70.
    Christian Schlünder et al. On the influence of BTI and HCI on parameter variability. In Reliability Physics Symposium (IRPS), 2017 IEEE International, pages 2E–4. IEEE, 2017.Google Scholar
  71. 71.
    Ann Mutschler. Transistor Aging Intensifies At 10/7nm And Below. https://semiengineering.com/transistor-aging-intensifies-10nm/, 2017. [Online; accessed 13-July-2017].
  72. 72.
    Ed Sperling. Chip Aging Accelerates. Semiconductor Engineering, 2018.Google Scholar
  73. 73.
    Jacopo Franco, Salvatore Graziano, Ben Kaczer, Felice Crupi, L-Å Ragnarsson, Tibor Grasser, and Guido Groeseneken. Bti reliability of ultra-thin eot mosfets for sub-threshold logic. Microelectronics Reliability, 52(9):1932–1935, 2012.CrossRefGoogle Scholar
  74. 74.
    Jeff Sather. Battery technologies for iot. In Enabling the Internet of Things, pages 409–440. Springer, 2017.Google Scholar
  75. 75.
    Scott Lerner and Baris Taskin. Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. In Quality Electronic Design (ISQED), 2017 18th International Symposium on, pages 379–384. IEEE, 2017.Google Scholar
  76. 76.
    Ajith Sivadasan, S Mhira, Armelle Notin, A Benhassain, V Huard, Etienne Maurin, F Cacho, L Anghel, and A Bravaix. Architecture-and workload-dependent digital failure rate. In Reliability Physics Symposium (IRPS), 2017 IEEE International, pages CR–8. IEEE, 2017.Google Scholar
  77. 77.
    Victor van Santen et al. Reliability in Super-and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV. TCAS-I, 2017.Google Scholar
  78. 78.
    Jayavardhana Gubbi, Rajkumar Buyya, Slaven Marusic, and Marimuthu Palaniswami. Internet of Things (IoT): A vision, architectural elements, and future directions. Future generation computer systems, 29(7):1645–1660, 2013.CrossRefGoogle Scholar
  79. 79.
    Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. Pulp: A parallel ultra low power platform for next generation iot applications. In Hot Chips 27 Symposium (HCS), 2015 IEEE, pages 1–39. IEEE, 2015.Google Scholar
  80. 80.
    T Grasser, M Waltl, G Rzepa, W Goes, Y Wimmer, A-M El-Sayed, AL Shluger, H Reisinger, and B Kaczer. The “permanent” component of nbti revisited: Saturation, degradation-reversal, and annealing. In Reliability Physics Symposium (IRPS), 2016 IEEE International, pages 5A–2. IEEE, 2016.Google Scholar
  81. 81.
    Minki Cho, Stephen T Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P Kulkarni, Krishnan Ravichandran, James W Tschanz, Muhammad M Khellah, and Vivek De. Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating. IEEE Journal of Solid-State Circuits, 52(1):50–63, 2017.CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Xinfei Guo
    • 1
  • Mircea R. Stan
    • 1
  1. 1.University of VirginiaCharlottesvilleUSA

Personalised recommendations