Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications

  • Xinfei Guo
  • Mircea R. Stan


The advent of FinFETs has extended the CMOS lifeline by a few more technology nodes (5 nm and even 3 nm are now under development), so it is critical for digital circuit designers and researchers to understand some of the fundamental differences between advanced FinFET nodes and older planar devices, along with the associated challenges (e.g., design and aging challenges) in the forthcoming sub-10 nm regime. This chapter consists of two major thrusts. In the first thrust, we present a comprehensive study that compares multiple technology nodes spanning from old planar devices to the most advanced FinFET nodes. This study adds to the FinFET design knowledge base and helps designers gain a thorough understanding of various design challenges. The second trust mainly looks at the impact of FinFET aging within the context of Internet of Things (IoT). Through extensive simulations with foundry-provided FinFET aging models, we conclude that aging can severely affect certain category of IoT applications; hence, this aspect needs to be incorporated in the design cycle to meet the overall system lifetime targets. Several candidate techniques against aging are also presented for designing robust IoT chips that perform faster, consume lower power, and last longer than without the use of these techniques.


FinFETs FDSOI VLSI Scaling Digital design IoT BTI HCI Lifetime Sleep mode Recovery 


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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Xinfei Guo
    • 1
  • Mircea R. Stan
    • 1
  1. 1.University of VirginiaCharlottesvilleUSA

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